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| datasheet r01ds0130ej0110 rev.1.10 page 1 of 105 dec 20, 2013 rx220 group renesas mcus features 32-bit rx cpu core ? max. operating frequency: 32 mhz ? capable of 49 dmips in operation at 32 mhz ? accumulator handles 64-bit results (for a single instruction) from 32- 32-bit operations ? multiplication and division unit handles 32- 32-bit operations (multiplication in structions take one cpu clock cycle) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instruc tions, ultra-compact code ? on-chip debugging circuit low-power design and architecture ? operation from a single 1.62-v to 5.5-v supply ? 1.62-v operation available (at up to 8 mhz) ? three low-power modes on-chip flash memory for code, no wait states ? 32-mhz operation, 31.25-ns read cycle ? no wait states for reading at full cpu speed ? up to 256-kbyte capacity ? user code programmable via the sci ? programmable at 1.62 v ? for instructions and operands on-chip data flash memory ? 8 kbytes (number of time s of reprogramming: 100,000) ? erasing and programming impose no load on the cpu. on-chip sram, no wait states ? up to 16-kbyte size capacity dma ? dmac: incorporates four channels ? dtc: four transfer modes elc ? module operation can be initiated by event signals without going through interrupts. ? modules can operate while the cpu is sleeping. reset and supply management ? seven types of reset, incl uding the power-on reset (por) ? low voltage detection (l vd) with voltage settings clock functions ? frequency of external clock: up to 20 mhz ? frequency of the oscillator for sub-clock generation: 32.768 khz ? on-chip low- and high-speed oscillators, dedicated on- chip low-speed oscillator for the iwdt ? generation of a dedicated 32.768-khz clock for the rtc ? clock frequency accuracy me asurement circuit (cac) real-time clock ? adjustment functions (30 se conds, leap year, and error) ? year and month display or 32- bit second display (binary counter) is selectable independent watchdog timer ? 125-khz on-chip oscillator pr oduces a dedicated clock signal to drive iwdt operation. useful functions for iec60730 compliance ? self-diagnostic and disconnect ion-detection assistance functions for the a/d c onverter, clock-frequency accuracy-measurement circ uit, independent watchdog timer, functions to assist in ram testing, etc. up to seven communications channels ? sci with many useful functions (up to five channels) asynchronous mode, clock synchronous mode, smart card interface mode ? irda interface (one channel, in cooperation with the sci5) ? i 2 c bus interface: transfer at up to 400 kbps, capable of smbus operation (one channel) ? rspi (one channel) up to 14 extend ed-function timers ? 16-bit mtu: input capt ure, output capture, complementary pwm output, phase counting mode (six channels) ? 8-bit tmr (four channels) ? 16-bit compare-match timers (four channels) 12-bit a/d converter ? capable of conversion within 1.56 s ? self-diagnostic function and analog input disconnection detection assist ance function analog comparator general i/o ports ? 5-v tolerant, open drain, input pull-up, switching of driving ability mpc ? multiple locations are selectable for i/o pins of peripheral functions operating temp. range ?? 40 ?c to +85 ?c ?? 40 ?c to +105 ?c plqp0100kb-a 14 14 mm, 0.5-mm pitch plqp0064kb-a 10 10 mm, 0.5-mm pitch plqp0048kb-a 7 7 mm, 0.5-mm pitch plqp0064ga-a 14 14 mm, 0.8-mm pitch 32-mhz 32-bit rx mcus, 49 dmips, up to 256-kb flash memory, 12-bit a/d, elc, mpc, irda, rtc, up to 7 comms channels; incorporating functions for iec60730 compliance r01ds0130ej0110 rev.1.10 dec 20, 2013
r01ds0130ej0110 rev.1.10 page 2 of 105 dec 20, 2013 rx220 group 1. overview 1. overview 1.1 outline of specifications table 1.1 lists the specifications in outline, and table 1.2 gives a comparison of the functions of products in different packages. table 1.1 is for products with the greatest number of functions , so numbers of peripheral modules and channels will differ in accord with the package. for details, see table 1.2, comparison of func tions for different packages . table 1.1 outline of specifications (1 / 3) classification module/function description cpu cpu ? maximum operating frequency: 32 mhz ? 32-bit rx cpu ? minimum instruction exec ution time: one instruction per st ate (cycle of the system clock) ? address space: 4-gbyte linear ? register general purpose: sixteen 32-bit registers control: eight 32-bit registers accumulator: one 64-bit register ? basic instructions: 73 ? dsp instructions: 9 ? addressing modes: 10 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32 ? 32 ? 64 bits ? on-chip divider: 32 / 32 ? 32 bits ? barrel shifter: 32 bits memory rom ? capacity: 32 k/64 k/128 k/256 kbytes ? 32 mhz, no-wait memory access ? on-board programming: 3 types ram ? capacity: 4 k/8 k/16 kbytes ? 32 mhz, no-wait memory access e2 dataflash e2 dataflash capacity: 8 kbytes mcu operating mode single-chip mode clock clock generation circuit ? main clock oscillator, sub-clock oscillator, low-s peed on-chip oscillator, high-speed on-chip oscillator, and iwdt-dedicated on-chip oscillator ? oscillation stop detection ? measuring circuit for accuracy of clo ck frequency (clock-accuracy check: cac) ? independent settings for the system clock (iclk), per ipheral module clock (pclk), and flashif clock (fclk) the cpu and system sections such as other bus masters run in synchronization with the system clock (iclk): 32 mhz (at max.) peripheral modules run in synchronization with the peripheral module clock (pclk): 32 mhz (at max.) the flash peripheral circuit runs in synchronization with the flash peripheral clock (fclk): 32 mhz (at max.) reset res# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset voltage detection voltage detection circuit (lvdaa) ? when the voltage on vcc falls below the voltage detection level, an internal reset or internal interrupt is generated. voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels low power consumption low power consumption facilities ? module stop function ? three low power consumption modes sleep mode, all-module clock stop mode, and software standby mode function for lower operating power consumption ? four operating power control modes middle-speed operating mode 1a, middle-speed operating mode 1b, low-speed operating mode 1, low-speed operating mode 2 interrupt interrupt controller (icub) ? interrupt vectors: 106 ? external interrupts: 9 (nmi, irq0 to irq7 pins) ? non-maskable interrupts: 5 (the nmi pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and iwdt interrupt) ? 16 levels specifiable for the order of priority r01ds0130ej0110 rev.1.10 page 3 of 105 dec 20, 2013 rx220 group 1. overview dma dma controller (dmaca) ? 4 channels ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: software trigger, external in terrupts, and interrupt requests from peripheral functions data transfer controller (dtca) ? three transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: interrupts ? chain transfer function i/o ports general i/o ports 100-pin/64-pin/48-pin ? i/o pin: 84/48/34 ? input: 1/1/1 ? pull-up resistors: 84/48/34 ? open-drain outputs: 35/26/20 ? 5-v tolerance: 4/2/2 ? 8-bit port switching function: not supported/supported/supported event link controller (elc) ? event signals of 46 types can be directly connected to the module ? operations of timer modules are selectable at event input ? capable of event link operation for port b multi-function pin controller (mpc) ? capable of selecting input/output function from multiple pins timers multi-function timer pulse unit 2 (mtu2a) ? (16 bits ? 6 channels) ? 1 unit ? time bases for the six 16-bit ti mer channels can be provided via up to 16 pulse-input/output lines and three pulse-input lines ? select from among eight or seven counter-input clock signals for each channel (pclk/1, pclk/4, pclk/16, pclk/64, pclk/256, pclk/1024, mt clka, mtclkb, mtclkc, mtclkd) other than channel 5, for which only four signals are available. ? input capture function ? 21 output compare/input capture registers ? pulse output mode ? complementary pwm output mode ? reset synchronous pwm mode ? phase-counting mode ? generation of triggers for a/d converter conversion port output enable 2 (poe2a) controls the high-impedance state of the mtu?s waveform output pins 8-bit timer (tmr) ? (8 bits ? 2 channels) ? 2 units ? select from among seven internal clock signals (pclk/1, pclk/2, pclk/8, pclk/32, pclk/64, pclk/1024, pclk/8192) and one external clock signal ? capable of output of pulse trains wi th desired duty cycles or of pwm signals ? the 2 channels of each unit can be cascaded to create a 16-bit timer ? capable of generating baud-rate clocks for sci5, sci6, and sci12 compare match timer (cmt) ? (16 bits ? 2 channels) ? 2 un its ? sel ect fr om among f our clock signals (pclk/8, pclk/32, pclk/128, pclk/512) independent watchdog timer (iwdta) ? 14 bits ? 1 channel ? counter-input clock: iwdt-dedicated on-chip oscillator frequency divided by 1, 16, 32, 64, 128, or 256 realtime clock (rtcc) ? clock source: sub-clock ? time count or 32-bit binary coun t in second units basis selectable ? time/calendar ? interrupt sources: alarm interrupt, periodic interrupt, and carry interrupt table 1.1 outline of specifications (2 / 3) classification module/function description r01ds0130ej0110 rev.1.10 page 4 of 105 dec 20, 2013 rx220 group 1. overview note 1. please contact renesas electronics sales office for derat ing of operation under ta = +85c to +105c. derating is the systematic reduction of load for th e sake of improved reliability. communication function serial communications interfaces (scie, scif) ? 5 channels (channel 1, 5, 6, and 9: scie, channe l 12: scif) (including one channel for irda) ? serial communications modes: asynchronous, clock synchronous, and smart-card interface ? on-chip baud rate generator allows selection of the desired bit rate ? choice of lsb-first or msb-first transfer ? average transfer rate clock can be input fr om tmr timers (sci5, sci6, and sci12) ? simple iic ? simple spi ? master/slave mode supported (scif only) ? start frame and information frame are included (scif only) ? detection of a start bit in asynchronous mode: low level or falling edge is selectable (scie/scif) irda interface (irda) ? 1 channel (sci5 is used) ? supports encoding/decoding the waveforms conf orming to the irda specification version 1.0 i 2 c bus interface (riic) ? 1 channel ? communications formats: i 2 c bus format/smbus format ? master/slave selectable ? supports the fast mode serial peripheral interface (rspi) ? 1 channel ? transfer facility using the mosi (master out, slave in), miso (master in, slave out), ssl (slave select), and rspck (rspi clock) signals enables serial transfer through spi operation (four lines) or clock-synchronous operation (three lines) ? capable of handling serial transfer as a master or slave ? data formats ? choice of lsb-first or msb-first transfer the number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or receiv ed in a single transfer operation (with each frame having up to 32 bits) ? double buffers for both transmission and reception 12-bit a/d converter (s12adb) ? 12 bits (16 channels ? 1 unit) ? 12-bit resolution ? minimum conversion time: 1.56 ? s per channel (in operation with adclk at 32 mhz) ? operating modes scan mode (single scan mode, continuous scan mode, and group scan mode) ? sample-and-hold function ? self-diagnosis for the a/d converter ? assistance in detecting disconnected analog inputs ? double-trigger mode (duplication of a/d conversion data) ? a/d conversion start conditions a software trigger, a trigger from a timer (mtu), an external trigger signal, or elc crc calculator (crc) ? crc code generation for any desired data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with lsb-firs t or msb-first communications is selectable. comparator a (cmpa) ? 2 channels ? comparison of reference voltage and analog input voltage data operation circuit (doc) comparison, addition, and subtraction of 16-bit data power supply voltage/operating frequency vcc = 1.62 to 2.7 v: 8 mhz, vcc = 2.7 to 5.5 v: 32 mhz operating temperature d version: ? 40 to +85c, g version: ? 40 to +105c* 1 package 100-pin lqfp (plqp0100kb-a) 64-pin lqfp (plqp0064kb-a) 64-pin lqfp (plqp0064ga-a) 48-pin lqfp (plqp0048kb-a) table 1.1 outline of specifications (3 / 3) classification module/function description r01ds0130ej0110 rev.1.10 page 5 of 105 dec 20, 2013 rx220 group 1. overview table 1.2 comparison of functions for different packages module/functions rx220 group 100 pins 64 pins 48 pins interrupt external interrupts nmi, irq0 to irq7 nmi, irq0 to irq2, irq4 to irq7 nmi, irq0, irq1, irq4 to irq7 dma dma controller 4 channels (dmac0 to dmac3) data transfer controller supported timers multi-function timer pulse unit 2 6 channels (mtu0 to mtu5) port output enable 2 poe0# to poe3#, poe8# 8-bit timer 2 channels 2 units compare match timer 2 channels 2 units realtime clock supported not supported independent watchdog timer supported communication function serial communications interface (scie) 4 channels (sci1, 5, 6, 9) (including one channel for irda) 3 channels (sci1, 5, 6) (including one channel for irda) serial communications interface (scif) 1 channel (sci12) i 2 c bus interface 1 channel serial peripheral interface 1 channel 12-bit a/d converter 16 channels (an000 to an015) 12 channels (an000 to an004, an006, an008 to an013) 8 channels (an000, an003, an004, an006, an009 to an012) crc calculator supported event link controller supported comparator a 2 channels 8-bit port switching function not supported in 100-pin packages supported in 64-pin packages switches pb6 to pc0 and pb7 to pc1 supported in 48-pin packages switches pb0 to pc0, pb1 to pc1, pb3 to pc2, and pb5 to pc3 package 100-pin lqfp 64-pin lqfp 48-pin lqfp r01ds0130ej0110 rev.1.10 page 6 of 105 dec 20, 2013 rx220 group 1. overview 1.2 list of products table 1.3 is a list of products, and figure 1.1 shows how to read the product pa rt no., memory capacity, and package type. note: ? please contact renesas electronics sales office for derat ing of operation under ta = +85c to +105c. derating is the systematic reduction of load for t he sake of improved reliability. table 1.3 list of products group part no. package rom capacity ram capacity operating frequency (max.) operating temperature rx220 r5f52206bdfp plqp0100kb-a 256 kbytes 16 kbytes 32 mhz ?40 to +85c r5f52206bdfm plqp0064kb-a r5f52206bdfk plqp0064ga-a r5f52206bdfl plqp0048kb-a r5f52205bdfp plqp0100kb-a 128 kbytes 8 kbytes r5f52205bdfm plqp0064kb-a r5f52205bdfk plqp0064ga-a r5f52205bdfl plqp0048kb-a r5f52203bdfp plqp0100kb-a 64 kbytes r5f52203bdfm plqp0064kb-a r5f52203bdfk plqp0064ga-a r5f52203bdfl plqp0048kb-a r5f52201bdfm plqp0064kb-a 32 kbytes 4kbytes r5f52201bdfk plqp0064ga-a r5f52201bdfl plqp0048kb-a r5f52206bgfp plqp0100kb-a 256 kbytes 16 kbytes 32 mhz ?40 to +105c r5f52206bgfm plqp0064kb-a r5f52206bgfk plqp0064ga-a r5f52206bgfl plqp0048kb-a r5f52205bgfp plqp0100kb-a 128 kbytes 8 kbytes r5f52205bgfm plqp0064kb-a r5f52205bgfk plqp0064ga-a r5f52205bgfl plqp0048kb-a r5f52203bgfp plqp0100kb-a 64 kbytes r5f52203bgfm plqp0064kb-a r5f52203bgfk plqp0064ga-a r5f52203bgfl plqp0048kb-a r5f52201bgfm plqp0064kb-a 32 kbytes 4kbytes r5f52201bgfk plqp0064ga-a r5f52201bgfl plqp0048kb-a r01ds0130ej0110 rev.1.10 page 7 of 105 dec 20, 2013 rx220 group 1. overview figure 1.1 how to read the product part no., memory capacity, and package type r5f52206bdfp package type, number of pins, and pin pitch fp: lqfp/100/0.50 fm: lqfp/64/0.50 fk: lqfp/64/0.80 fl: lqfp/48/0.50 d: operating temperature (?40 to +85c) g: operating temperature (?40 to +105c) rom, ram, and e2 dataflash capacity 6: 256 kbytes/16 kbytes/8 kbytes 5: 128 kbytes/8 kbytes/8 kbytes 3: 64 kbytes/8 kbytes/8 kbytes 1: 32 kbytes/4 kbytes/8 kbytes group name 20: rx220 group series name rx200 series type of memory f: flash memory version renesas mcu renesas semiconductor product r01ds0130ej0110 rev.1.10 page 8 of 105 dec 20, 2013 rx220 group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram bsc icub: interrupt controller dtca: data transfer controller dmaca: dma controller bsc: bus controller iwdta: independent watchdog timer elc: event link controller crc: crc (cyclic redundancy check) calculator scie, scif: serial communications interface irda: infrared data association rspi: serial peripheral interface riic: i 2 c bus interface mtu2a: multi-function timer pulse unit 2 poe2a: port output enable 2 tmr: 8-bit timer cmt: compare match timer rtcc: realtime clock doc: data operation circuit cac: clock-frequency accu racy measuring circuit operand bus instruction bus internal main bus 1 clock generation circuit rx cpu ram rom internal peripheral buses 1 to 6 internal main bus 2 dtca dmaca 4 channels icub port e port j e2 dataflash iwdta elc crc scie 4 channels (including one channel for irda) rspi 1 channel riic 1 channel mtu2a 6 channels poe2a tmr 2 channels (unit 1) tmr 2 channels (unit 0) 12-bit a/d converter 16 channels doc comparator a 2 channels cac port 0 port 1 port 2 port 3 port 4 port 5 port a port b port c cmt 2 channels (unit 1) cmt 2 channels (unit 0) port d port h rtcc scif 1 channel r01ds0130ej0110 rev.1.10 page 9 of 105 dec 20, 2013 rx220 group 1. overview 1.4 pin functions table 1.4 lists the pin functions. table 1.4 pin functions (1 / 3) classifications pin name i/o description power supply vcc input power supply pin. connect it to the system power supply. vcl ? connect this pin to the vss pin via the 0.1 f smoothing capacitor used to stabilize the internal power supply. place the capacitor close to the pin. vss input ground pin. connect it to the system power supply (0 v). clock xtal output pins for connecting a crystal resonator. an external clock signal can be input through the extal pin. extal input xcin input input/output pins for the sub-clock generation circuit. connect a crystal resonator between xcin and xcout. xcout output operating mode control md input pin for setting the operating mode. the signal levels on this pin must not be changed during operation. system control res# input reset signal input pin. this lsi enters the reset state when this signal goes low. cac cacref input input pin for the measuri ng circuit for cloc k frequency precision. on-chip emulator fined i/o fine interface pin. interrupt nmi input non-maskable interrupt request pin. irq0 to irq7 input interrupt request pins. multi-function timer pulse unit mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/ pwm output pins. mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/ pwm output pins. mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/ pwm output pins. mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/ pwm output pins. mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/ pwm output pins. mtic5u, mtic5v, mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/external pulse input pins. mtclka, mtclkb, mtclkc, mtclkd input input pins for external clock. port output enable poe0# to poe3#, poe8# input input pins for request signals to place the mtu pins in the high impedance state. 8-bit timer tmo0 to tmo3 output compare match output pins. tmci0 to tmci3 input input pins for external clocks to be input to the counter. tmri0 to tmri3 input input pins for the counter reset. realtime clock rtcout output output pin for 1-hz clock. r01ds0130ej0110 rev.1.10 page 10 of 105 dec 20, 2013 rx220 group 1. overview serial communications interface (scie) ? asynchronous mode/clock synchronous mode sck1, sck5, sck6, sck9 i/o input/output pins for clock rxd1, rxd5, rxd6, rxd9 input input pins for received data txd1, txd5, txd6, txd9 output output pins for transmitted data cts1#, cts5#, cts6#, cts9# input input pins for controlling the start of transmission and reception rts1#, rts5#, rts6#, rts9# output output pins for controlling th e start of transmission and reception ? simple i 2 c mode sscl1, sscl5, sscl6, sscl9 i/o input/output pins for the i 2 c clock ssda1, ssda5, ssda6, ssda9 i/o input/output pins for the i 2 c data ? simple spi mode sck1, sck5, sck6, sck9 i/o input/output pins for the clock smiso1, smiso5, smiso6, smiso9 i/o input/output pins for slave transmission of data smosi1, smosi5, smosi6, smosi9 i/o input/output pins for master transmission of data ss1#, ss5#, ss6#, ss9# input chip-select input pins ? irda interface irtxd5 output data output pin in the irda format irrxd5 input data input pin in the irda format serial communications interface (scif) ? asynchronous mode/clock synchronous mode sck12 i/o input/output pin for the clock rxd12 input input pin for received data txd12 output output pin for transmitted data cts12# input input pin for controlling the start of transmission and reception rts12# output output pin for controlling the start of transmission and reception ? simple i 2 c mode sscl12 i/o input/output pin for the i 2 c clock ssda12 i/o input/output pin for the i 2 c data ? simple spi mode sck12 i/o input/output pin for the clock smiso12 i/o input/output pin for slave transmit data smosi12 i/o input/output pin for master transmit data ss12# input chip-select input pin ? extended serial mode rxdx12 input input pin for data reception by scif txdx12 output output pin for data transmission by scif siox12 i/o input/output pin for data reception or transmission by scif i 2 c bus interface scl i/o input/output pin for i 2 c bus interface clocks . bus can be directly driven by the n-channel open-drain output. sda i/o input/output pin for i 2 c bus interface data. bus can be directly driven by the n-channel open-drain output. table 1.4 pin functions (2 / 3) classifications pin name i/o description r01ds0130ej0110 rev.1.10 page 11 of 105 dec 20, 2013 rx220 group 1. overview serial peripheral interface rspcka i/o clock input/output pin for the rspi. mosia i/o input or output data output from the master for the rspi. misoa i/o input or output data output from the slave for the rspi. ssla0 i/o input/output pin to select the slave for the rspi. ssla1 to ssla3 output output pins to select the slave for the rspi. 12-bit a/d converter an000 to an015 input input pin for the analog signals to be processed by the a/d converter. adtrg0# input input pin for the external trigger signals that start the a/d conversion. comparator a cmpa1 input input analog pin for the comparator a1. cmpa2 input input analog pin for the comparator a2. cvrefa input input pin for the comparator reference voltage. analog power supply avcc0 input analog voltage supply pin for t he 12-bit a/d converter. connect this pin to vcc if the 12-bit a/d converter is not to be used. avss0 input analog ground pin for the 12-bit a/d converter. connect this pin to vss if the 12-bit a/d converter is not to be used. vrefh0 input analog reference voltage supply pin for the 12-bit a/d converter. connect this pin to vcc if the 12-bit a/d converter is not to be used. vrefl0 input analog reference ground pin for the 12-bit a/d converter. connect this pin to vss if the 12-bit a/d converter is not to be used. i/o ports p03, p05, p07 i/o 3-bit input/output pins. p12 to p17 i/o 6-bit input/output pins. p20 to p27 i/o 8-bit input/output pins. p30 to p37 i/o 8-bit input/output pins. (p35 input pin) p40 to p47 i/o 8-bit input/output pins. p50 to p55 i/o 6-bit input/output pins. pa0 to pa7 i/o 8-bit input/output pins. pb0 to pb7 i/o 8-bit input/output pins. pc0 to pc7 i/o 8-bit input/output pins. pd0 to pd7 i/o 8-bit input/output pins. pe0 to pe7 i/o 8-bit input/output pins. ph0 to ph3 i/o 4-bit input/output pins. pj1, pj3 i/o 2-bit input/output pins. table 1.4 pin functions (3 / 3) classifications pin name i/o description r01ds0130ej0110 rev.1.10 page 12 of 105 dec 20, 2013 rx220 group 1. overview 1.5 pin assignments figure 1.3 to figure 1.5 show the pin assignments. table 1.5 to table 1.7 show the lists of pins and pin functions. figure 1.3 pin assignments of the 100-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 pe0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 p47 p46 p45 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p07 avss0 pe1 p44 pc2 pc4 pc5 pc6 pc7 p50 p51 p52 p53 p54 p55 ph0 ph1 ph3 p12 p13 p14 p15 p16 p17 p20 p21 p22 pc3 ph2 pe3 pe5 pe6 pe7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 vss vcc pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pe4 pb0 nc nc pj3 vcl pj1 md xcin xcout res# p37/xtal vss p36/extal p35 p34 p33 p32 p31 p30 p27 p26 p25 p23 p03 vcc pe2 p05 p24 rx220 group plqp0100kb-a (100-pin lqfp) (top view) note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (100-pin lqfp)?. r01ds0130ej0110 rev.1.10 page 13 of 105 dec 20, 2013 rx220 group 1. overview figure 1.4 pin assignments of the 64-pin lqfp figure 1.5 pin assignments of the 48-pin lqfp 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx220 group plqp0064kb-a plqp0064ga-a (64-pin lqfp) (top view) pe2 pe1 pe0 nc p46 nc p44 p43 p42 p41 vrefl0 p40 vrefh0 avcc0 p05 avss0 pe3 pe4 pe5 pa0 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pb6/pc0 pb7/pc1 pc2 pc3 pc4 pc5 pc6 pc7 p54 p55 ph0 ph1 ph2 ph3 p14 p15 p16 p17 p03 vcl md xcin xcout res# p37/xtal vss p36/extal vcc p35 p32 p31 p30 p27 p26 note: ? this figure indicates the power supply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functions (64-pin lqfp)?. 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 38 39 37 40 41 42 43 44 45 47 48 46 rx220 group plqp0048kb-a (48-pin lqfp) (top view) pe2 pe1 nc p46 nc p42 p41 vrefl0 p40 vrefh0 avcc0 avss0 pe3 pe4 pa1 pa3 pa4 pa6 vss pb0/pc0 vcc pb1/pc1 pb3/pc2 pb5/pc3 pc4 pc5 pc6 pc7 ph0 ph1 ph2 ph3 p14 p15 p16 p17 vcl md res# p37/xtal vss p36/extal vcc p35 p31 p30 p27 p26 18 17 16 15 14 13 note: ? this figure indicates the power s upply pins and i/o port pins. for the pin configuration, see the table ?list of pins and pin functi ons (48-pin lqfp)?. r01ds0130ej0110 rev.1.10 page 14 of 105 dec 20, 2013 rx220 group 1. overview table 1.5 list of pins and pin functions (100-pin lqfp) (1 / 3) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scie, scif, rspi, riic) others 1 nc (non-connection) 2p 0 3 3 nc (non-connection) 4 pj3 mtioc3c cts6#/rts6#/ss6# 5vcl 6p j 1 m t i o c 3 a 7md fined 8xcin 9 xcout 10 res# 11 xtal p37 12 vss 13 extal p36 14 vcc 15 p35 nmi 16 p34 mtioc0a/tmci3/poe2# sck6 irq4 17 p33 mtioc0d/tmri3/poe3# rxd6/smiso6/sscl6 irq3 18 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 irq2/rtcout 19 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1 20 p30 mtioc4b/tmri3/poe8# rxd1/smiso1/sscl1 irq0 21 p27 mtioc2b/tmci3 sck1 22 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 23 p25 mtioc4c/mtclkb adtrg0# 24 p24 mtioc4a/mtclka/tmri1 25 p23 mtioc3d/mtclkd 26 p22 mtioc3b/mtclkc/tmo0 27 p21 mtioc1b/tmci0 28 p20 mtioc1a/tmri0 29 p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda irq7 30 p16 mtioc3c/mtioc3d/tmo2 txd1/smosi1/ssda1/mosia/ scl irq6/rtcout/adtrg0# 31 p15 mtioc0b/mtclkb/tmci 2 rxd1/smiso1/sscl1 irq5 32 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# irq4 33 p13 mtioc0b/tmo3 sda irq3 34 p12 tmci1 scl irq2 35 ph3 tmci0 36 ph2 tmri0 irq1 37 ph1 tmo0 irq0 38 ph0 cacref 39 p55 mtioc4d/tmo3 40 p54 mtioc4b/tmci1 41 p53 42 p52 43 p51 44 p50 45 pc7 mtioc3a/tmo2/mtclkb misoa cacref 46 pc6 mtioc3c/mtclka/tmci2 mosia 47 pc5 mtioc3b/mtclkd/tmri2 rspcka r01ds0130ej0110 rev.1.10 page 15 of 105 dec 20, 2013 rx220 group 1. overview 48 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/ssla0 49 pc3 mtioc4d txd5/smosi5/ssda5/irtxd5 50 pc2 mtioc4b rxd5/s miso5/sscl5/irrxd5/ ssla3 51 pc1 mtioc3a sck5/ssla2 52 pc0 mtioc3c cts5#/rts5#/ss5#/ssla1 53 pb7 mtioc3b txd9/smosi9/ssda9 54 pb6 mtioc3d rxd9/smiso9/sscl9 55 pb5 mtioc2a/mtioc1b/tmri1/ poe1# sck9 56 pb4 cts9#/rts9#/ss9# 57 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6 58 pb2 cts6#/rts6#/ss6# 59 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 irq4 60 vcc 61 pb0 mtic5w rxd6/smiso6/sscl6/rspcka 62 vss 63 pa7 misoa 64 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia 65 pa5 rspcka 66 pa4 mtic5u/mtclka/tmri0 txd5/smosi5/ssda5/irtxd5/ ssla0 irq5 67 pa3 mtioc0d/mtclkd rxd5/smiso5/sscl5/irrxd5 irq6 68 pa2 rxd5/smiso5/sscl5/ssla3/ irrxd5 69 pa1 mtioc0b/mtclkc sck5/ssla2 cvrefa 70 pa0 mtioc4a ssla1 cacref 71 pe7 irq7/an015 72 pe6 irq6/an014 73 pe5 mtioc4c/mtioc2b irq5/an013 74 pe4 mtioc4d/mtioc1a an012/cmpa2 75 pe3 mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 76 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12 irq7/an010 77 pe1 mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009 78 pe0 sck12 an008 79 pd7 mtic5u/poe0# irq7 80 pd6 mtic5v/poe1# irq6 81 pd5 mtic5w/poe2# irq5 82 pd4 poe3# irq4 83 pd3 poe8# irq3 84 pd2 mtioc4d irq2 85 pd1 mtioc4b irq1 86 pd0 irq0 87 p47 an007 88 p46 an006 89 p45 an005 90 p44 an004 table 1.5 list of pins and pin functions (100-pin lqfp) (2 / 3) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scie, scif, rspi, riic) others r01ds0130ej0110 rev.1.10 page 16 of 105 dec 20, 2013 rx220 group 1. overview 91 p43 an003 92 p42 an002 93 p41 an001 94 vrefl0 95 p40 an000 96 vrefh0 97 avcc0 98 p07 adtrg0# 99 avss0 100 p05 table 1.5 list of pins and pin functions (100-pin lqfp) (3 / 3) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scie, scif, rspi, riic) others r01ds0130ej0110 rev.1.10 page 17 of 105 dec 20, 2013 rx220 group 1. overview table 1.6 list of pins and pin functions (64-pin lqfp) (1 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communication (scie, scif, rspi, riic) others 1p 0 3 2vcl 3md fined 4xcin 5 xcout 6 res# 7xtal p37 8 vss 9 extal p36 10 vcc 11 p35 nmi 12 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 irq2/rtcout 13 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1 14 p30 mtioc4b/tmri3/poe8# rxd1/smiso1/sscl1 irq0 15 p27 mtioc2b/tmci3 sck1 16 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 17 p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda irq7 18 p16 mtioc3c/mtioc3d/tmo2 txd1/smosi1/ssda1/mosia/ scl irq6/rtcout/adtrg0# 19 p15 mtioc0b/mtclkb/tmci 2 rxd1/smiso1/sscl1 irq5 20 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# irq4 21 ph3 tmci0 22 ph2 tmri0 irq1 23 ph1 tmo0 irq0 24 ph0 cacref 25 p55 mtioc4d/tmo3 26 p54 mtioc4b/tmci1 27 pc7 mtioc3a/tmo2/mtclkb misoa cacref 28 pc6 mtioc3c/mtclka/tmci2 mosia 29 pc5 mtioc3b/mtclkd/tmri2 rspcka 30 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/ssla0 31 pc3 mtioc4d txd5/smosi5/ssda5/irtxd5 32 pc2 mtioc4b rxd5/s miso5/sscl5/irrxd5/ ssla3 33 pb7/pc1 mtioc3b txd9/smosi9/ssda9 34 pb6/pc0 mtioc3d rxd9/smiso9/sscl9 35 pb5 mtioc2a/mtioc1b/tmri1/ poe1# sck9 36 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6 37 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 irq4 38 vcc 39 pb0 mtic5w rxd6/smiso6/sscl6/rspcka 40 vss 41 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia 42 pa4 mtic5u/mtclka/tmri0 txd5/smosi5/ssda5/irtxd5/ ssla0 irq5 43 pa3 mtioc0d/mtclkd rxd5/smiso5/sscl5/irrxd5 irq6 r01ds0130ej0110 rev.1.10 page 18 of 105 dec 20, 2013 rx220 group 1. overview 44 pa1 mtioc0b/mtclkc sck5/ssla2 cvrefa 45 pa0 mtioc4a ssla1 cacref 46 pe5 mtioc4c/mtioc2b irq5/an013 47 pe4 mtioc4d/mtioc1a an012/cmpa2 48 pe3 mtioc4b/poe8# cts12#/rts12#/ss12# an011/cmpa1 49 pe2 mtioc4a rxd12/rxdx12/smiso12/ sscl12 irq7/an010 50 pe1 mtioc4c txd12/txdx12/siox12/ smosi12/ssda12 an009 51 pe0 sck12 an008 52 nc (non-connection) 53 p46 an006 54 nc (non-connection) 55 p44 an004 56 p43 an003 57 p42 an002 58 p41 an001 59 vrefl0 60 p40 an000 61 vrefh0 62 avcc0 63 p05 64 avss0 table 1.6 list of pins and pin functions (64-pin lqfp) (2 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communication (scie, scif, rspi, riic) others r01ds0130ej0110 rev.1.10 page 19 of 105 dec 20, 2013 rx220 group 1. overview table 1.7 list of pins and pin functions (48-pin lqfp) (1 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communication (scie, scif, rspi, riic) others 1v c l 2m d fined 3r e s # 4x t a l p 3 7 5v s s 6 extal p36 7v c c 8p 3 5 nmi 9 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# irq1 10 p30 mtioc4b/tmri3/poe8# rxd1/smiso1/sscl1 irq0 11 p27 mtioc2b/tmci3 sck1 12 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 13 p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda irq7 14 p16 mtioc3c/mtioc3d/tmo2 t xd1/smosi1/ssda1/mosia/ scl irq6/adtrg0# 15 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 irq5 16 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# irq4 17 ph3 tmci0 18 ph2 tmri0 irq1 19 ph1 tmo0 irq0 20 ph0 cacref 21 pc7 mtioc3a/tmo2/mtclkb misoa cacref 22 pc6 mtioc3c/mtclka/tmci2 mosia 23 pc5 mtioc3b/mtclkd/tmri2 rspcka 24 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/ssla0 25 pb5/pc3 mtioc2a/mtioc1b/tmri1/ poe1# 26 pb3/pc2 mtioc0a/mtioc4a/tmo0/ poe3# sck6 27 pb1/pc1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 irq4 28 vcc 29 pb0/pc0 mtic5w rxd6/smiso6/sscl6/rspcka 30 vss 31 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia 32 pa4 mtic5u/mtclka/tmri0 txd5/smosi5/ssda5/irtxd5/ ssla0 irq5 33 pa3 mtioc0d/mtclkd rxd5/smiso5/sscl5/irrxd5 irq6 34 pa1 mtioc0b/mtclkc sck5/ssla2 cvrefa 35 pe4 mtioc4d/mtioc1a an012/cmpa2 36 pe3 mtioc4b/poe8# cts12#/rts12# an011/cmpa1 37 pe2 mtioc4a rxd12/rxdx12/sscl12 irq7/an010 38 pe1 mtioc4c txd12/txdx12/siox12/ ssda12 an009 39 nc (non-connection) 40 p46 an006 41 nc (non-connection) 42 p42 an002 43 p41 an001 r01ds0130ej0110 rev.1.10 page 20 of 105 dec 20, 2013 rx220 group 1. overview 44 vrefl0 45 p40 an000 46 vrefh0 47 avcc0 48 avss0 table 1.7 list of pins and pin functions (48-pin lqfp) (2 / 2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communication (scie, scif, rspi, riic) others r01ds0130ej0110 rev.1.10 page 21 of 105 dec 20, 2013 rx220 group 2. cpu 2. cpu figure 2.1 shows the register set of the cpu. figure 2.1 register set of the cpu note 1. the stack pointer (sp) can be the interrupt stack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw register. usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) *1 general-purpose register control register b31 b0 b31 b0 dsp instruction register b63 b0 acc (accumulator) r01ds0130ej0110 rev.1.10 page 22 of 105 dec 20, 2013 rx220 group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has sixteen general-purpose registers (r0 to r15). r1 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by th e value of the stack pointer se lect bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (i sp)/user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). set the isp or usp to a multiple of four, as this reduces th e numbers of cycles required to execute interrupt sequences and instructions entai ling stack manipulation. (2) interrupt table register (intb) the interrupt table register (intb) specifies the address where the relocatable vector table starts. (3) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (4) processor status word (psw) the processor status word (psw) i ndicates the results of instruction execution or the state of the cpu. (5) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc register. (6) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (7) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated. 2.3 register associated with dsp instructions (1) accumulator (acc) the accumulator (acc) is a 64-bit register used for dsp instru ctions. the accumulator is also used for the multiply and multiply-and-accumulate inst ructions; emul, emulu, mul, and rmpa, in which case the prior value in the accumulator is modified by execution of the instruction. use the mvtachi and mvtaclo instructions for wr iting to the accumulator. the mvtachi and mvtaclo instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfachi and mvfacmi instructions for reading data from th e accumulator. the mvfachi and mvfacmi instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively. r01ds0130ej0110 rev.1.10 page 23 of 105 dec 20, 2013 rx220 group 3. address space 3. address space 3.1 address space this lsi has a 4-gbyte address space, consisting of the rang e of addresses from 0000 0000 h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory map. r01ds0130ej0110 rev.1.10 page 24 of 105 dec 20, 2013 rx220 group 3. address space figure 3.1 memory map 0000 0000h 0008 0000h ffff ffffh single-chip mode* 1 0010 0000h 0010 2000h 0080 0000h 0100 0000h fffc 0000h ff7f c000h 007f c000h 007f c500h 007f fc00h 0000 4000h ff80 0000h 00fc 0000h reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 reserved area* 3 on-chip rom (e2 dataflash) (8 kb) reserved area* 3 ram* 2 on-chip rom (program rom) (read only)* 2 peripheral i/o registers on-chip rom (program rom) (write only) (256 kb) on-chip rom (user boot) (read only) (16 kb) peripheral i/o registers peripheral i/o registers note 1. the address space in boot mode and user boot mode is the same as the address space in single-chip mode. note 2. the capacity of rom/ram differs depending on the products. note:?see table 1.3, list of products, for the product type name. note 3. reserved areas should not be accessed. rom (bytes) ram (bytes) capacity address capacity address 256 k fffc 0000h to ffff ffffh 16 k 0000 0000h to 0000 3fffh 128 k fffe 0000h to ffff ffffh 8 k 0000 0000h to 0000 1fffh 64k ffff 0000h to ffff ffffh 32 k ffff 8000h to ffff ffffh 4 k 0000 0000h to 0000 0fffh r01ds0130ej0110 rev.1.10 page 25 of 105 dec 20, 2013 rx220 group 4. i/o registers 4. i/o registers this section provides information on the on-chip i/o register addresses and bit configuration. the information is given as shown below. notes on writing to registers are also given below. (1) i/o register addresses (address order) ? registers are listed from th e lower allocation addresses. ? registers are classified acco rding to module symbols. ? numbers of cycles for access indicate numbers of cycles of the given base clock. ? among the internal i/o register area, a ddresses not listed in the list of regi sters are reserved. reserved addresses must not be accessed. do not access these addresses; ot herwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers when writing to an i/o register , the cpu starts executing the subsequent instru ction before completing i/o register write. this may cause the subsequent instruction to be executed befo re the post-update i/o register value is reflected on the operation. as described in the following examples, sp ecial care is required for the cases in wh ich the subsequent instruction must be executed after the post-update i/o re gister value is actually reflected. [examples of cases requiring special care] ? the subsequent instruction must be execu ted while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request en able bit) cleared to 0. ? a wait instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value from the i/o re gister to a general register. (c) execute the operati on using the value read. (d) execute the subsequent instruction. [instruction examples] ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process r01ds0130ej0110 rev.1.10 page 26 of 105 dec 20, 2013 rx220 group 4. i/o registers ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process if multiple registers are written to and a subsequent instruc tion should be executed after th e write operati ons are entirely completed, only read the i/o register that was last written to and execute the operation using th e value; it is not necessary to read or execute operation for all the registers that were written to. (3) number of access cycles to i/o registers for numbers of clock cycles fo r access to i/o registers, see table 4.1, list of i/o registers (address order) . the number of access cycles to i/o regist ers is obtained by following equation. * 1 number of access cycles to i/o registers = numb er of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for internal peripheral bus 1 to 6 the number of bus cycles of internal peripheral bus 1 to 6 differs according to the register to be accessed. when peripheral functions connected to internal peripheral bus 2 to 6 ar e accessed, the number of divided clock synchronization cycles is added. the number of divided clock synchronization cycles differs depending on the frequency ratio between iclk and pclk (or fclk) or bus access timing. in the peripheral function unit, when the fr equency ratio of iclk is equal to or gr eater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pclk (or fclk) has been added to the number of access cycles shown in table 4.1 . when the frequency ratio of iclk is lower than that of pclk (or fclk), the subsequent bus access is started from the iclk cycle following the completion of the access to the peripheral functions. th erefore, the access cycles are described on an iclk basis. note 1. this applies to the nu mber of cycles when the access from the cpu does not conflict with the instruction bus access from the different bus master (dmac or dtc). r01ds0130ej0110 rev.1.10 page 27 of 105 dec 20, 2013 rx220 group 4. i/o registers 4.1 i/o register addresses (address order) table 4.1 list of i/o register s (address order) (1 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk 0008 0000h system mode monitor register mdmonr 16 16 3 iclk 0008 0002h system mode status register mdsr 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk 0008 0010h system module stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 iclk 0008 0026h system system clock control register 3 sckcr3 16 16 3 iclk 0008 0032h system main clock oscillator control register mosccr 8 8 3 iclk 0008 0033h system sub-clock oscillator control register sosccr 8 8 3 iclk 0008 0035h system iwdt-dedicated on-chip oscillator control register ilococr 8 8 3 iclk 0008 0036h system high-speed on-chip oscillator control register hococr 8 8 3 iclk 0008 0037h system high-speed on-chip oscillator control register 2 hococr2 8 8 3 iclk 0008 0040h system oscillation stop detection control register ostdcr 8 8 3 iclk 0008 0041h system oscillation stop detection status register ostdsr 8 8 3 iclk 0008 00a0h system operating power control register opccr 8 8 3 iclk 0008 00a1h system sleep mode return clock source switching register rstckcr 8 8 3 iclk 0008 00a2h system main clock oscillator wait control register moscwtcr 8 8 3 iclk 0008 00a3h system sub-clock oscillator wait control register soscwtcr 8 8 3 iclk 0008 00a9h system hoco wait control register 2 hocowtcr2 8 8 3 iclk 0008 00c0h system reset status register 2 rstsr2 8 8 3 iclk 0008 00c2h system software reset register swrr 16 16 3 iclk 0008 00e0h system voltage monitoring 1 circuit/comparator a1 control register 1 lvd1cr1 8 8 3 iclk 0008 00e1h system voltage monitoring 1 circuit/comparator a1 status register lvd1sr 8 8 3 iclk 0008 00e2h system voltage monitoring 2 circuit/comparator a2 control register 1 lvd2cr1 8 8 3 iclk 0008 00e3h system voltage monitoring 2 circuit/comparator a2 status register lvd2sr 8 8 3 iclk 0008 03feh system protect register prcr 16 16 3 iclk 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 1310h bsc bus priority control register buspri 16 16 2 iclk 0008 2000h dmac0 dma source address register dmsar 32 32 2 iclk 0008 2004h dmac0 dma destination address register dmdar 32 32 2 iclk 0008 2008h dmac0 dma transfer count register dmcra 32 32 2 iclk 0008 200ch dmac0 dma block transfer count register dmcrb 16 16 2 iclk 0008 2010h dmac0 dma transfer mode register dmtmd 16 16 2 iclk 0008 2013h dmac0 dma interrupt setting register dmint 8 8 2 iclk 0008 2014h dmac0 dma address mode register dmamd 16 16 2 iclk 0008 2018h dmac0 dma offset register dmofr 32 32 2 iclk 0008 201ch dmac0 dma transfer enable register dmcnt 8 8 2 iclk 0008 201dh dmac0 dma software start register dmreq 8 8 2 iclk 0008 201eh dmac0 dma status register dmsts 8 8 2 iclk 0008 201fh dmac0 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2040h dmac1 dma source address register dmsar 32 32 2 iclk 0008 2044h dmac1 dma destination address register dmdar 32 32 2 iclk 0008 2048h dmac1 dma transfer count register dmcra 32 32 2 iclk 0008 204ch dmac1 dma block transfer count register dmcrb 16 16 2 iclk r01ds0130ej0110 rev.1.10 page 28 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 2050h dmac1 dma transfer mode register dmtmd 16 16 2 iclk 0008 2053h dmac1 dma interrupt setting register dmint 8 8 2 iclk 0008 2054h dmac1 dma address mode register dmamd 16 16 2 iclk 0008 205ch dmac1 dma transfer enable register dmcnt 8 8 2 iclk 0008 205dh dmac1 dma software start register dmreq 8 8 2 iclk 0008 205eh dmac1 dma status register dmsts 8 8 2 iclk 0008 205fh dmac1 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2080h dmac2 dma source address register dmsar 32 32 2 iclk 0008 2084h dmac2 dma destination address register dmdar 32 32 2 iclk 0008 2088h dmac2 dma transfer count register dmcra 32 32 2 iclk 0008 208ch dmac2 dma block transfer count register dmcrb 16 16 2 iclk 0008 2090h dmac2 dma transfer mode register dmtmd 16 16 2 iclk 0008 2093h dmac2 dma interrupt setting register dmint 8 8 2 iclk 0008 2094h dmac2 dma address mode register dmamd 16 16 2 iclk 0008 209ch dmac2 dma transfer enable register dmcnt 8 8 2 iclk 0008 209dh dmac2 dma software start register dmreq 8 8 2 iclk 0008 209eh dmac2 dma status register dmsts 8 8 2 iclk 0008 209fh dmac2 dma activation source flag control register dmcsl 8 8 2 iclk 0008 20c0h dmac3 dma source address register dmsar 32 32 2 iclk 0008 20c4h dmac3 dma destination address register dmdar 32 32 2 iclk 0008 20c8h dmac3 dma transfer count register dmcra 32 32 2 iclk 0008 20cch dmac3 dma block transfer count register dmcrb 16 16 2 iclk 0008 20d0h dmac3 dma transfer mode register dmtmd 16 16 2 iclk 0008 20d3h dmac3 dma interrupt setting register dmint 8 8 2 iclk 0008 20d4h dmac3 dma address mode register dmamd 16 16 2 iclk 0008 20dch dmac3 dma transfer enable register dmcnt 8 8 2 iclk 0008 20ddh dmac3 dma software start register dmreq 8 8 2 iclk 0008 20deh dmac3 dma status register dmsts 8 8 2 iclk 0008 20dfh dmac3 dma activation source flag control register dmcsl 8 8 2 iclk 0008 2200h dmac dma module activation register dmast 8 8 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2 iclk 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk 0008 7010h icu interrupt request register 016 ir016 8 8 2 iclk 0008 7015h icu interrupt request register 021 ir021 8 8 2 iclk 0008 7017h icu interrupt request register 023 ir023 8 8 2 iclk 0008 701bh icu interrupt request register 027 ir027 8 8 2 iclk 0008 701ch icu interrupt request register 028 ir028 8 8 2 iclk 0008 701dh icu interrupt request register 029 ir029 8 8 2 iclk 0008 701eh icu interrupt request register 030 ir030 8 8 2 iclk 0008 701fh icu interrupt request register 031 ir031 8 8 2 iclk 0008 7020h icu interrupt request register 032 ir032 8 8 2 iclk 0008 7021h icu interrupt request register 033 ir033 8 8 2 iclk 0008 7022h icu interrupt request register 034 ir034 8 8 2 iclk 0008 702ch icu interrupt request register 044 ir044 8 8 2 iclk 0008 702dh icu interrupt request register 045 ir045 8 8 2 iclk 0008 702eh icu interrupt request register 046 ir046 8 8 2 iclk 0008 702fh icu interrupt request register 047 ir047 8 8 2 iclk 0008 7039h icu interrupt request register 057 ir057 8 8 2 iclk table 4.1 list of i/o register s (address order) (2 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 29 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 703fh icu interrupt request register 063 ir063 8 8 2 iclk 0008 7040h icu interrupt request register 064 ir064 8 8 2 iclk 0008 7041h icu interrupt request register 065 ir065 8 8 2 iclk 0008 7042h icu interrupt request register 066 ir066 8 8 2 iclk 0008 7043h icu interrupt request register 067 ir067 8 8 2 iclk 0008 7044h icu interrupt request register 068 ir068 8 8 2 iclk 0008 7045h icu interrupt request register 069 ir069 8 8 2 iclk 0008 7046h icu interrupt request register 070 ir070 8 8 2 iclk 0008 7047h icu interrupt request register 071 ir071 8 8 2 iclk 0008 7058h icu interrupt request register 088 ir088 8 8 2 iclk 0008 7059h icu interrupt request register 089 ir089 8 8 2 iclk 0008 705ch icu interrupt request register 092 ir092 8 8 2 iclk 0008 705dh icu interrupt request register 093 ir093 8 8 2 iclk 0008 7066h icu interrupt request register 102 ir102 8 8 2 iclk 0008 7067h icu interrupt request register 103 ir103 8 8 2 iclk 0008 706ah icu interrupt request register 106 ir106 8 8 2 iclk 0008 7072h icu interrupt request register 114 ir114 8 8 2 iclk 0008 7073h icu interrupt request register 115 ir115 8 8 2 iclk 0008 7074h icu interrupt request register 116 ir116 8 8 2 iclk 0008 7075h icu interrupt request register 117 ir117 8 8 2 iclk 0008 7076h icu interrupt request register 118 ir118 8 8 2 iclk 0008 7077h icu interrupt request register 119 ir119 8 8 2 iclk 0008 7078h icu interrupt request register 120 ir120 8 8 2 iclk 0008 7079h icu interrupt request register 121 ir121 8 8 2 iclk 0008 707ah icu interrupt request register 122 ir122 8 8 2 iclk 0008 707bh icu interrupt request register 123 ir123 8 8 2 iclk 0008 707ch icu interrupt request register 124 ir124 8 8 2 iclk 0008 707dh icu interrupt request register 125 ir125 8 8 2 iclk 0008 707eh icu interrupt request register 126 ir126 8 8 2 iclk 0008 707fh icu interrupt request register 127 ir127 8 8 2 iclk 0008 7080h icu interrupt request register 128 ir128 8 8 2 iclk 0008 7081h icu interrupt request register 129 ir129 8 8 2 iclk 0008 7082h icu interrupt request register 130 ir130 8 8 2 iclk 0008 7083h icu interrupt request register 131 ir131 8 8 2 iclk 0008 7084h icu interrupt request register 132 ir132 8 8 2 iclk 0008 7085h icu interrupt request register 133 ir133 8 8 2 iclk 0008 7086h icu interrupt request register 134 ir134 8 8 2 iclk 0008 7087h icu interrupt request register 135 ir135 8 8 2 iclk 0008 7088h icu interrupt request register 136 ir136 8 8 2 iclk 0008 7089h icu interrupt request register 137 ir137 8 8 2 iclk 0008 708ah icu interrupt request register 138 ir138 8 8 2 iclk 0008 708bh icu interrupt request register 139 ir139 8 8 2 iclk 0008 708ch icu interrupt request register 140 ir140 8 8 2 iclk 0008 708dh icu interrupt request register 141 ir141 8 8 2 iclk 0008 70aah icu interrupt request register 170 ir170 8 8 2 iclk 0008 70abh icu interrupt request register 171 ir171 8 8 2 iclk 0008 70aeh icu interrupt request register 174 ir174 8 8 2 iclk 0008 70afh icu interrupt request register 175 ir175 8 8 2 iclk 0008 70b0h icu interrupt request register 176 ir176 8 8 2 iclk 0008 70b1h icu interrupt request register 177 ir177 8 8 2 iclk 0008 70b2h icu interrupt request register 178 ir178 8 8 2 iclk table 4.1 list of i/o register s (address order) (3 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 30 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 70b3h icu interrupt request register 179 ir179 8 8 2 iclk 0008 70b4h icu interrupt request register 180 ir180 8 8 2 iclk 0008 70b5h icu interrupt request register 181 ir181 8 8 2 iclk 0008 70b6h icu interrupt request register 182 ir182 8 8 2 iclk 0008 70b7h icu interrupt request register 183 ir183 8 8 2 iclk 0008 70b8h icu interrupt request register 184 ir184 8 8 2 iclk 0008 70b9h icu interrupt request register 185 ir185 8 8 2 iclk 0008 70c6h icu interrupt request register 198 ir198 8 8 2 iclk 0008 70c7h icu interrupt request register 199 ir199 8 8 2 iclk 0008 70c8h icu interrupt request register 200 ir200 8 8 2 iclk 0008 70c9h icu interrupt request register 201 ir201 8 8 2 iclk 0008 70dah icu interrupt request register 218 ir218 8 8 2 iclk 0008 70dbh icu interrupt request register 219 ir219 8 8 2 iclk 0008 70dch icu interrupt request register 220 ir220 8 8 2 iclk 0008 70ddh icu interrupt request register 221 ir221 8 8 2 iclk 0008 70deh icu interrupt request register 222 ir222 8 8 2 iclk 0008 70dfh icu interrupt request register 223 ir223 8 8 2 iclk 0008 70e0h icu interrupt request register 224 ir224 8 8 2 iclk 0008 70e1h icu interrupt request register 225 ir225 8 8 2 iclk 0008 70e2h icu interrupt request register 226 ir226 8 8 2 iclk 0008 70e3h icu interrupt request register 227 ir227 8 8 2 iclk 0008 70e4h icu interrupt request register 228 ir228 8 8 2 iclk 0008 70e5h icu interrupt request register 229 ir229 8 8 2 iclk 0008 70eah icu interrupt request register 234 ir234 8 8 2 iclk 0008 70ebh icu interrupt request register 235 ir235 8 8 2 iclk 0008 70ech icu interrupt request register 236 ir236 8 8 2 iclk 0008 70edh icu interrupt request register 237 ir237 8 8 2 iclk 0008 70eeh icu interrupt request register 238 ir238 8 8 2 iclk 0008 70efh icu interrupt request register 239 ir239 8 8 2 iclk 0008 70f0h icu interrupt request register 240 ir240 8 8 2 iclk 0008 70f1h icu interrupt request register 241 ir241 8 8 2 iclk 0008 70f2h icu interrupt request register 242 ir242 8 8 2 iclk 0008 70f3h icu interrupt request register 243 ir243 8 8 2 iclk 0008 70f4h icu interrupt request register 244 ir244 8 8 2 iclk 0008 70f5h icu interrupt request register 245 ir245 8 8 2 iclk 0008 70f6h icu interrupt request register 246 ir246 8 8 2 iclk 0008 70f7h icu interrupt request register 247 ir247 8 8 2 iclk 0008 70f8h icu interrupt request register 248 ir248 8 8 2 iclk 0008 70f9h icu interrupt request register 249 ir249 8 8 2 iclk 0008 711bh icu dtc activation enable register 027 dtcer027 8 8 2 iclk 0008 711ch icu dtc activation enable register 028 dtcer028 8 8 2 iclk 0008 711dh icu dtc activation enable register 029 dtcer029 8 8 2 iclk 0008 711eh icu dtc activation enable register 030 dtcer030 8 8 2 iclk 0008 711fh icu dtc activation enable register 031 dtcer031 8 8 2 iclk 0008 712dh icu dtc activation enable register 045 dtcer045 8 8 2 iclk 0008 712eh icu dtc activation enable register 046 dtcer046 8 8 2 iclk 0008 7140h icu dtc activation enable register 064 dtcer064 8 8 2 iclk 0008 7141h icu dtc activation enable register 065 dtcer065 8 8 2 iclk 0008 7142h icu dtc activation enable register 066 dtcer066 8 8 2 iclk 0008 7143h icu dtc activation enable register 067 dtcer067 8 8 2 iclk 0008 7144h icu dtc activation enable register 068 dtcer068 8 8 2 iclk table 4.1 list of i/o register s (address order) (4 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 31 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 7145h icu dtc activation enable register 069 dtcer069 8 8 2 iclk 0008 7146h icu dtc activation enable register 070 dtcer070 8 8 2 iclk 0008 7147h icu dtc activation enable register 071 dtcer071 8 8 2 iclk 0008 7166h icu dtc activation enable register 102 dtcer102 8 8 2 iclk 0008 7167h icu dtc activation enable register 103 dtcer103 8 8 2 iclk 0008 716ah icu dtc activation enable register 106 dtcer106 8 8 2 iclk 0008 7172h icu dtc activation enable register 114 dtcer114 8 8 2 iclk 0008 7173h icu dtc activation enable register 115 dtcer115 8 8 2 iclk 0008 7174h icu dtc activation enable register 116 dtcer116 8 8 2 iclk 0008 7175h icu dtc activation enable register 117 dtcer117 8 8 2 iclk 0008 7179h icu dtc activation enable register 121 dtcer121 8 8 2 iclk 0008 717ah icu dtc activation enable register 122 dtcer122 8 8 2 iclk 0008 717dh icu dtc activation enable register 125 dtcer125 8 8 2 iclk 0008 717eh icu dtc activation enable register 126 dtcer126 8 8 2 iclk 0008 7181h icu dtc activation enable register 129 dtcer129 8 8 2 iclk 0008 7182h icu dtc activation enable register 130 dtcer130 8 8 2 iclk 0008 7183h icu dtc activation enable register 131 dtcer131 8 8 2 iclk 0008 7184h icu dtc activation enable register 132 dtcer132 8 8 2 iclk 0008 7186h icu dtc activation enable register 134 dtcer134 8 8 2 iclk 0008 7187h icu dtc activation enable register 135 dtcer135 8 8 2 iclk 0008 7188h icu dtc activation enable register 136 dtcer136 8 8 2 iclk 0008 7189h icu dtc activation enable register 137 dtcer137 8 8 2 iclk 0008 718ah icu dtc activation enable register 138 dtcer138 8 8 2 iclk 0008 718bh icu dtc activation enable register 139 dtcer139 8 8 2 iclk 0008 718ch icu dtc activation enable register 140 dtcer140 8 8 2 iclk 0008 718dh icu dtc activation enable register 141 dtcer141 8 8 2 iclk 0008 71aeh icu dtc activation enable register 174 dtcer174 8 8 2 iclk 0008 71afh icu dtc activation enable register 175 dtcer175 8 8 2 iclk 0008 71b1h icu dtc activation enable register 177 dtcer177 8 8 2 iclk 0008 71b2h icu dtc activation enable register 178 dtcer178 8 8 2 iclk 0008 71b4h icu dtc activation enable register 180 dtcer180 8 8 2 iclk 0008 71b5h icu dtc activation enable register 181 dtcer181 8 8 2 iclk 0008 71b7h icu dtc activation enable register 183 dtcer183 8 8 2 iclk 0008 71b8h icu dtc activation enable register 184 dtcer184 8 8 2 iclk 0008 71c6h icu dtc activation enable register 198 dtcer198 8 8 2 iclk 0008 71c7h icu dtc activation enable register 199 dtcer199 8 8 2 iclk 0008 71c8h icu dtc activation enable register 200 dtcer200 8 8 2 iclk 0008 71c9h icu dtc activation enable register 201 dtcer201 8 8 2 iclk 0008 71dbh icu dtc activation enable register 219 dtcer219 8 8 2 iclk 0008 71dch icu dtc activation enable register 220 dtcer220 8 8 2 iclk 0008 71dfh icu dtc activation enable register 223 dtcer223 8 8 2 iclk 0008 71e0h icu dtc activation enable register 224 dtcer224 8 8 2 iclk 0008 71e3h icu dtc activation enable register 227 dtcer227 8 8 2 iclk 0008 71e4h icu dtc activation enable register 228 dtcer228 8 8 2 iclk 0008 71ebh icu dtc activation enable register 235 dtcer235 8 8 2 iclk 0008 71ech icu dtc activation enable register 236 dtcer236 8 8 2 iclk 0008 71efh icu dtc activation enable register 239 dtcer239 8 8 2 iclk 0008 71f0h icu dtc activation enable register 240 dtcer240 8 8 2 iclk 0008 71f7h icu dtc activation enable register 247 dtcer247 8 8 2 iclk 0008 71f8h icu dtc activation enable register 248 dtcer248 8 8 2 iclk 0008 7202h icu interrupt request enable register 02 ier02 8 8 2 iclk table 4.1 list of i/o register s (address order) (5 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 32 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 7203h icu interrupt request enable register 03 ier03 8 8 2 iclk 0008 7204h icu interrupt request enable register 04 ier04 8 8 2 iclk 0008 7205h icu interrupt request enable register 05 ier05 8 8 2 iclk 0008 7207h icu interrupt request enable register 07 ier07 8 8 2 iclk 0008 7208h icu interrupt request enable register 08 ier08 8 8 2 iclk 0008 720bh icu interrupt request enable register 0b ier0b 8 8 2 iclk 0008 720ch icu interrupt request enable register 0c ier0c 8 8 2 iclk 0008 720dh icu interrupt request enable register 0d ier0d 8 8 2 iclk 0008 720eh icu interrupt request enable register 0e ier0e 8 8 2 iclk 0008 720fh icu interrupt request enable register 0f ier0f 8 8 2 iclk 0008 7210h icu interrupt request enable register 10 ier10 8 8 2 iclk 0008 7211h icu interrupt request enable register 11 ier11 8 8 2 iclk 0008 7215h icu interrupt request enable register 15 ier15 8 8 2 iclk 0008 7216h icu interrupt request enable register 16 ier16 8 8 2 iclk 0008 7217h icu interrupt request enable register 17 ier17 8 8 2 iclk 0008 7218h icu interrupt request enable register 18 ier18 8 8 2 iclk 0008 7219h icu interrupt request enable register 19 ier19 8 8 2 iclk 0008 721bh icu interrupt request enable register 1b ier1b 8 8 2 iclk 0008 721ch icu interrupt request enable register 1c ier1c 8 8 2 iclk 0008 721dh icu interrupt request enable register 1d ier1d 8 8 2 iclk 0008 721eh icu interrupt request enable register 1e ier1e 8 8 2 iclk 0008 721fh icu interrupt request enable register 1f ier1f 8 8 2 iclk 0008 72e0h icu software interrupt activation register swintr 8 8 2 iclk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h icu interrupt source priority register 000 ipr000 8 8 2 iclk 0008 7301h icu interrupt source priority register 001 ipr001 8 8 2 iclk 0008 7302h icu interrupt source priority register 002 ipr002 8 8 2 iclk 0008 7303h icu interrupt source priority register 003 ipr003 8 8 2 iclk 0008 7304h icu interrupt source priority register 004 ipr004 8 8 2 iclk 0008 7305h icu interrupt source priority register 005 ipr005 8 8 2 iclk 0008 7306h icu interrupt source priority register 006 ipr006 8 8 2 iclk 0008 7307h icu interrupt source priority register 007 ipr007 8 8 2 iclk 0008 7320h icu interrupt source priority register 032 ipr032 8 8 2 iclk 0008 7321h icu interrupt source priority register 033 ipr033 8 8 2 iclk 0008 7322h icu interrupt source priority register 034 ipr034 8 8 2 iclk 0008 732ch icu interrupt source priority register 044 ipr044 8 8 2 iclk 0008 7339h icu interrupt source priority register 057 ipr057 8 8 2 iclk 0008 733fh icu interrupt source priority register 063 ipr063 8 8 2 iclk 0008 7340h icu interrupt source priority register 064 ipr064 8 8 2 iclk 0008 7341h icu interrupt source priority register 065 ipr065 8 8 2 iclk 0008 7342h icu interrupt source priority register 066 ipr066 8 8 2 iclk 0008 7343h icu interrupt source priority register 067 ipr067 8 8 2 iclk 0008 7344h icu interrupt source priority register 068 ipr068 8 8 2 iclk 0008 7345h icu interrupt source priority register 069 ipr069 8 8 2 iclk 0008 7346h icu interrupt source priority register 070 ipr070 8 8 2 iclk 0008 7347h icu interrupt source priority register 071 ipr071 8 8 2 iclk 0008 7358h icu interrupt source priority register 088 ipr088 8 8 2 iclk 0008 7359h icu interrupt source priority register 089 ipr089 8 8 2 iclk 0008 735ch icu interrupt source priority register 092 ipr092 8 8 2 iclk 0008 735dh icu interrupt source priority register 093 ipr093 8 8 2 iclk 0008 7366h icu interrupt source priority register 102 ipr102 8 8 2 iclk table 4.1 list of i/o register s (address order) (6 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 33 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 7367h icu interrupt source priority register 103 ipr103 8 8 2 iclk 0008 736ah icu interrupt source priority register 106 ipr106 8 8 2 iclk 0008 7372h icu interrupt source priority register 114 ipr114 8 8 2 iclk 0008 7376h icu interrupt source priority register 118 ipr118 8 8 2 iclk 0008 7379h icu interrupt source priority register 121 ipr121 8 8 2 iclk 0008 737bh icu interrupt source priority register 123 ipr123 8 8 2 iclk 0008 737dh icu interrupt source priority register 125 ipr125 8 8 2 iclk 0008 737fh icu interrupt source priority register 127 ipr127 8 8 2 iclk 0008 7381h icu interrupt source priority register 129 ipr129 8 8 2 iclk 0008 7385h icu interrupt source priority register 133 ipr133 8 8 2 iclk 0008 7386h icu interrupt source priority register 134 ipr134 8 8 2 iclk 0008 738ah icu interrupt source priority register 138 ipr138 8 8 2 iclk 0008 738bh icu interrupt source priority register 139 ipr139 8 8 2 iclk 0008 73aah icu interrupt source priority register 170 ipr170 8 8 2 iclk 0008 73abh icu interrupt source priority register 171 ipr171 8 8 2 iclk 0008 73aeh icu interrupt source priority register 174 ipr174 8 8 2 iclk 0008 73b1h icu interrupt source priority register 177 ipr177 8 8 2 iclk 0008 73b4h icu interrupt source priority register 180 ipr180 8 8 2 iclk 0008 73b7h icu interrupt source priority register 183 ipr183 8 8 2 iclk 0008 73c6h icu interrupt source priority register 198 ipr198 8 8 2 iclk 0008 73c7h icu interrupt source priority register 199 ipr199 8 8 2 iclk 0008 73c8h icu interrupt source priority register 200 ipr200 8 8 2 iclk 0008 73c9h icu interrupt source priority register 201 ipr201 8 8 2 iclk 0008 73dah icu interrupt source priority register 218 ipr218 8 8 2 iclk 0008 73deh icu interrupt source priority register 222 ipr222 8 8 2 iclk 0008 73e2h icu interrupt source priority register 226 ipr226 8 8 2 iclk 0008 73eah icu interrupt source priority register 234 ipr234 8 8 2 iclk 0008 73eeh icu interrupt source priority register 238 ipr238 8 8 2 iclk 0008 73f2h icu interrupt source priority register 242 ipr242 8 8 2 iclk 0008 73f3h icu interrupt source priority register 243 ipr243 8 8 2 iclk 0008 73f4h icu interrupt source priority register 244 ipr244 8 8 2 iclk 0008 73f5h icu interrupt source priority register 245 ipr245 8 8 2 iclk 0008 73f6h icu interrupt source priority register 246 ipr246 8 8 2 iclk 0008 73f7h icu interrupt source priority register 247 ipr247 8 8 2 iclk 0008 73f8h icu interrupt source priority register 248 ipr248 8 8 2 iclk 0008 73f9h icu interrupt source priority register 249 ipr249 8 8 2 iclk 0008 7400h icu dmac activation request select register 0 dmrsr0 8 8 2 iclk 0008 7404h icu dmac activation request select register 1 dmrsr1 8 8 2 iclk 0008 7408h icu dmac activation request select register 2 dmrsr2 8 8 2 iclk 0008 740ch icu dmac activation request select register 3 dmrsr3 8 8 2 iclk 0008 7500h icu irq control register 0 irqcr0 8 8 2 iclk 0008 7501h icu irq control register 1 irqcr1 8 8 2 iclk 0008 7502h icu irq control register 2 irqcr2 8 8 2 iclk 0008 7503h icu irq control register 3 irqcr3 8 8 2 iclk 0008 7504h icu irq control register 4 irqcr4 8 8 2 iclk 0008 7505h icu irq control register 5 irqcr5 8 8 2 iclk 0008 7506h icu irq control register 6 irqcr6 8 8 2 iclk 0008 7507h icu irq control register 7 irqcr7 8 8 2 iclk 0008 7510h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk 0008 7514h icu irq pin digital filter setting register 0 irqfltc0 16 16 2 iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk table 4.1 list of i/o register s (address order) (7 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 34 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk 0008 7582h icu non-maskable interrupt clear register nmiclr 8 8 2 iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2, 3 pclkb 2 iclk 0008 8002h cmt0 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 8004h cmt0 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 8006h cmt0 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8008h cmt1 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 800ah cmt1 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 800ch cmt1 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8010h cmt compare match timer start register 1 cmstr1 16 16 2, 3 pclkb 2 iclk 0008 8012h cmt2 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 8014h cmt2 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 8016h cmt2 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8018h cmt3 compare match timer control register cmcr 16 16 2, 3 pclkb 2 iclk 0008 801ah cmt3 compare match timer counter cmcnt 16 16 2, 3 pclkb 2 iclk 0008 801ch cmt3 compare match timer constant register cmcor 16 16 2, 3 pclkb 2 iclk 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2, 3 pclkb 2 iclk 0008 8032h iwdt iwdt control register iwdtcr 16 16 2, 3 pclkb 2 iclk 0008 8034h iwdt iwdt status register iwdtsr 16 16 2, 3 pclkb 2 iclk 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2, 3 pclkb 2 iclk 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2, 3 pclkb 2 iclk 0008 8200h tmr0 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8201h tmr1 timer counter control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8202h tmr0 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk 0008 8203h tmr1 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk 0008 8204h tmr0 time constant register a tcora 8 8 2, 3 pclkb 2 iclk 0008 8205h tmr1 time constant register a tcora 8 8* 1 2, 3 pclkb 2 iclk 0008 8206h tmr0 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk 0008 8207h tmr1 time constant register b tcorb 8 8* 1 2, 3 pclkb 2 iclk 0008 8208h tmr0 timer counter tcnt 8 8 2, 3 pclkb 2 iclk 0008 8209h tmr1 timer counter tcnt 8 8* 1 2, 3 pclkb 2 iclk 0008 820ah tmr0 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk 0008 820bh tmr1 timer counter control register tccr 8 8* 1 2, 3 pclkb 2 iclk 0008 820ch tmr0 time count start register tcstr 8 8 2, 3 pclkb 2 iclk 0008 8210h tmr2 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8211h tmr3 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8212h tmr2 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk 0008 8213h tmr3 timer control/status register tcsr 8 8 2, 3 pclkb 2 iclk 0008 8214h tmr2 time constant register a tcora 8 8 2, 3 pclkb 2 iclk 0008 8215h tmr3 time constant register a tcora 8 8* 1 2, 3 pclkb 2 iclk 0008 8216h tmr2 time constant register b tcorb 8 8 2, 3 pclkb 2 iclk 0008 8217h tmr3 time constant register b tcorb 8 8* 1 2, 3 pclkb 2 iclk 0008 8218h tmr2 timer counter tcnt 8 8 2, 3 pclkb 2 iclk 0008 8219h tmr3 timer counter tcnt 8 8* 1 2, 3 pclkb 2 iclk 0008 821ah tmr2 timer counter control register tccr 8 8 2, 3 pclkb 2 iclk 0008 821bh tmr3 timer counter control register tccr 8 8* 1 2, 3 pclkb 2 iclk 0008 821ch tmr2 time count start register tcstr 8 8 2, 3 pclkb 2 iclk 0008 8280h crc crc control register crccr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (8 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 35 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 8281h crc crc data input register crcdir 8 8 2, 3 pclkb 2 iclk 0008 8282h crc crc data output register crcdor 16 16 2, 3 pclkb 2 iclk 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2, 3 pclkb 2 iclk 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2, 3 pclkb 2 iclk 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2, 3 pclkb 2 iclk 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2, 3 pclkb 2 iclk 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2, 3 pclkb 2 iclk 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2, 3 pclkb 2 iclk 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2, 3 pclkb 2 iclk 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2, 3 pclkb 2 iclk 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2, 3 pclkb 2 iclk 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2, 3 pclkb 2 iclk 0008 830ah riic0 slave address register l0 sarl0 8 8 2, 3 pclkb 2 iclk 0008 830ah riic0 timeout internal counter l tmocntl 8 8 2, 3 pclkb 2 iclk 0008 830bh riic0 slave address register u0 saru0 8 8 2, 3 pclkb 2 iclk 0008 830bh riic0 timeout internal counter u tmocntu 8 8* 2 2, 3 pclkb 2 iclk 0008 830ch riic0 slave address register l1 sarl1 8 8 2, 3 pclkb 2 iclk 0008 830dh riic0 slave address register u1 saru1 8 8 2, 3 pclkb 2 iclk 0008 830eh riic0 slave address register l2 sarl2 8 8 2, 3 pclkb 2 iclk 0008 830fh riic0 slave address register u2 saru2 8 8 2, 3 pclkb 2 iclk 0008 8310h riic0 i 2 c bus bit rate low-level register icbrl 8 8 2, 3 pclkb 2 iclk 0008 8311h riic0 i 2 c bus bit rate high-level register icbrh 8 8 2, 3 pclkb 2 iclk 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2, 3 pclkb 2 iclk 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2, 3 pclkb 2 iclk 0008 8380h rspi0 rspi control register spcr 8 8 2, 3 pclkb 2 iclk 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2, 3 pclkb 2 iclk 0008 8382h rspi0 rspi pin control register sppcr 8 8 2, 3 pclkb 2 iclk 0008 8383h rspi0 rspi status register spsr 8 8 2, 3 pclkb 2 iclk 0008 8384h rspi0 rspi data register spdr 32 16, 32 2, 3 pclkb 2 iclk 0008 8388h rspi0 rspi sequence control register spscr 8 8 2, 3 pclkb 2 iclk 0008 8389h rspi0 rspi sequence status register spssr 8 8 2, 3 pclkb 2 iclk 0008 838ah rspi0 rspi bit rate register spbr 8 8 2, 3 pclkb 2 iclk 0008 838bh rspi0 rspi data control register spdcr 8 8 2, 3 pclkb 2 iclk 0008 838ch rspi0 rspi clock delay register spckd 8 8 2, 3 pclkb 2 iclk 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2, 3 pclkb 2 iclk 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2, 3 pclkb 2 iclk 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2, 3 pclkb 2 iclk 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2, 3 pclkb 2 iclk 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2, 3 pclkb 2 iclk 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2, 3 pclkb 2 iclk 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2, 3 pclkb 2 iclk 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2, 3 pclkb 2 iclk 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2, 3 pclkb 2 iclk 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2, 3 pclkb 2 iclk 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2, 3 pclkb 2 iclk 0008 8410h irda irda control register ircr 8 8 2, 3 pclkb 2 iclk 0008 8600h mtu3 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8601h mtu4 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8602h mtu3 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8603h mtu4 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8604h mtu3 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (9 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 36 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 8605h mtu3 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk 0008 8606h mtu4 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk 0008 8607h mtu4 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk 0008 8608h mtu3 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8609h mtu4 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 860ah mtu timer output master enable register toer 8 8 2, 3 pclkb 2 iclk 0008 860dh mtu timer gate control register tgcr 8 8 2, 3 pclkb 2 iclk 0008 860eh mtu timer output control register 1 tocr1 8 8 2, 3 pclkb 2 iclk 0008 860fh mtu timer output control register 2 tocr2 8 8 2, 3 pclkb 2 iclk 0008 8610h mtu3 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8612h mtu4 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8614h mtu timer cycle data register tcdr 16 16 2, 3 pclkb 2 iclk 0008 8616h mtu timer dead time data register tddr 16 16 2, 3 pclkb 2 iclk 0008 8618h mtu3 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 861ah mtu3 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 861ch mtu4 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 861eh mtu4 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8620h mtu timer subcounter tcnts 16 16 2, 3 pclkb 2 iclk 0008 8622h mtu timer cycle buffer register tcbr 16 16 2, 3 pclkb 2 iclk 0008 8624h mtu3 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 8626h mtu3 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 8628h mtu4 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 862ah mtu4 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 862ch mtu3 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 862dh mtu4 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8630h mtu timer interrupt skipping set register titcr 8 8 2, 3 pclkb 2 iclk 0008 8631h mtu timer interrupt skipping counter titcnt 8 8 2, 3 pclkb 2 iclk 0008 8632h mtu timer buffer transfer set register tbter 8 8 2, 3 pclkb 2 iclk 0008 8634h mtu timer dead time enable register tder 8 8 2, 3 pclkb 2 iclk 0008 8636h mtu timer output level buffer register tolbr 8 8 2, 3 pclkb 2 iclk 0008 8638h mtu3 timer buffer operation transfer mode register tbtm 8 8 2, 3 pclkb 2 iclk 0008 8639h mtu4 timer buffer operation transfer mode register tbtm 8 8 2, 3 pclkb 2 iclk 0008 8640h mtu4 timer a/d converter start request control register tadcr 16 16 2, 3 pclkb 2 iclk 0008 8644h mtu4 timer a/d converter start request cycle set register a tadcora 16 16 2, 3 pclkb 2 iclk 0008 8646h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 2, 3 pclkb 2 iclk 0008 8648h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16 2, 3 pclkb 2 iclk 0008 864ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 2, 3 pclkb 2 iclk 0008 8660h mtu timer waveform control register twcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8680h mtu timer start register tstr 8 8, 16 2, 3 pclkb 2 iclk 0008 8681h mtu timer synchronous register tsyr 8 8, 16 2, 3 pclkb 2 iclk 0008 8684h mtu timer read/write enable register trwer 8 8, 16 2, 3 pclkb 2 iclk 0008 8690h mtu0 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8691h mtu1 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8692h mtu2 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8693h mtu3 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8694h mtu4 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8695h mtu5 noise filter control register nfcr 8 8, 16 2, 3 pclkb 2 iclk 0008 8700h mtu0 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8701h mtu0 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8702h mtu0 timer i/o control register h tiorh 8 8 2, 3 pclkb 2 iclk 0008 8703h mtu0 timer i/o control register l tiorl 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (10 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 37 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 8704h mtu0 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8705h mtu0 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8706h mtu0 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8708h mtu0 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 870ah mtu0 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 870ch mtu0 timer general register c tgrc 16 16 2, 3 pclkb 2 iclk 0008 870eh mtu0 timer general register d tgrd 16 16 2, 3 pclkb 2 iclk 0008 8720h mtu0 timer general register e tgre 16 16 2, 3 pclkb 2 iclk 0008 8722h mtu0 timer general register f tgrf 16 16 2, 3 pclkb 2 iclk 0008 8724h mtu0 timer interrupt enable register 2 tier2 8 8 2, 3 pclkb 2 iclk 0008 8726h mtu0 timer buffer operation transfer mode register tbtm 8 8 2, 3 pclkb 2 iclk 0008 8780h mtu1 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8781h mtu1 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8782h mtu1 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk 0008 8784h mtu1 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8785h mtu1 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8786h mtu1 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8788h mtu1 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 878ah mtu1 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8790h mtu1 timer input capture control register ticcr 8 8 2, 3 pclkb 2 iclk 0008 8800h mtu2 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 8801h mtu2 timer mode register tmdr 8 8 2, 3 pclkb 2 iclk 0008 8802h mtu2 timer i/o control register tior 8 8 2, 3 pclkb 2 iclk 0008 8804h mtu2 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 8805h mtu2 timer status register tsr 8 8 2, 3 pclkb 2 iclk 0008 8806h mtu2 timer counter tcnt 16 16 2, 3 pclkb 2 iclk 0008 8808h mtu2 timer general register a tgra 16 16 2, 3 pclkb 2 iclk 0008 880ah mtu2 timer general register b tgrb 16 16 2, 3 pclkb 2 iclk 0008 8880h mtu5 timer counter u tcntu 16 16 2, 3 pclkb 2 iclk 0008 8882h mtu5 timer general register u tgru 16 16 2, 3 pclkb 2 iclk 0008 8884h mtu5 timer control register u tcru 8 8 2, 3 pclkb 2 iclk 0008 8886h mtu5 timer i/o control register u tioru 8 8 2, 3 pclkb 2 iclk 0008 8890h mtu5 timer counter v tcntv 16 16 2, 3 pclkb 2 iclk 0008 8892h mtu5 timer general register v tgrv 16 16 2, 3 pclkb 2 iclk 0008 8894h mtu5 timer control register v tcrv 8 8 2, 3 pclkb 2 iclk 0008 8896h mtu5 timer i/o control register v tiorv 8 8 2, 3 pclkb 2 iclk 0008 88a0h mtu5 timer counter w tcntw 16 16 2, 3 pclkb 2 iclk 0008 88a2h mtu5 timer general register w tgrw 16 16 2, 3 pclkb 2 iclk 0008 88a4h mtu5 timer control register w tcrw 8 8 2, 3 pclkb 2 iclk 0008 88a6h mtu5 timer i/o control register w tiorw 8 8 2, 3 pclkb 2 iclk 0008 88b2h mtu5 timer interrupt enable register tier 8 8 2, 3 pclkb 2 iclk 0008 88b4h mtu5 timer start register tstr 8 8 2, 3 pclkb 2 iclk 0008 88b6h mtu5 timer compare match clear register tcntcmpclr 8 8 2, 3 pclkb 2 iclk 0008 8900h poe input level control/status register 1 icsr1 16 8, 16 2, 3 pclkb 2 iclk 0008 8902h poe output level control/status register 1 ocsr1 16 8, 16 2, 3 pclkb 2 iclk 0008 8908h poe input level control/status register 2 icsr2 16 8, 16 2, 3 pclkb 2 iclk 0008 890ah poe software port output enable register spoer 8 8 2, 3 pclkb 2 iclk 0008 890bh poe port output enable control register 1 poecr1 8 8 2, 3 pclkb 2 iclk 0008 890ch poe port output enable control register 2 poecr2 8 8 2, 3 pclkb 2 iclk 0008 890eh poe input level control/status register 3 icsr3 16 8, 16 2, 3 pclkb 2 iclk 0008 9000h s12ad a/d control register adcsr 16 16 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (11 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 38 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 9004h s12ad a/d channel select register a adansa 16 16 2, 3 pclkb 2 iclk 0008 9008h s12ad a/d-converted value addition mode select register adads 16 16 2, 3 pclkb 2 iclk 0008 900ch s12ad a/d-converted value addition count select register adadc 8 8 2, 3 pclkb 2 iclk 0008 900eh s12ad a/d control extended register adcer 16 16 2, 3 pclkb 2 iclk 0008 9010h s12ad a/d start trigger select register adstrgr 16 16 2, 3 pclkb 2 iclk 0008 9012h s12ad a/d converted extended input control register adexicr 16 16 2, 3 pclkb 2 iclk 0008 9014h s12ad a/d channel select register b adansb 16 16 2, 3 pclkb 2 iclk 0008 9018h s12ad a/d double register addbldr 16 16 2, 3 pclkb 2 iclk 0008 901ch s12ad a/d internal reference voltage data register adocdr 16 16 2, 3 pclkb 2 iclk 0008 901eh s12ad a/d self-diagnosis data register adrd 16 16 2, 3 pclkb 2 iclk 0008 9020h s12ad a/d data register 0 addr0 16 16 2, 3 pclkb 2 iclk 0008 9022h s12ad a/d data register 1 addr1 16 16 2, 3 pclkb 2 iclk 0008 9024h s12ad a/d data register 2 addr2 16 16 2, 3 pclkb 2 iclk 0008 9026h s12ad a/d data register 3 addr3 16 16 2, 3 pclkb 2 iclk 0008 9028h s12ad a/d data register 4 addr4 16 16 2, 3 pclkb 2 iclk 0008 902ah s12ad a/d data register 5 addr5 16 16 2, 3 pclkb 2 iclk 0008 902ch s12ad a/d data register 6 addr6 16 16 2, 3 pclkb 2 iclk 0008 902eh s12ad a/d data register 7 addr7 16 16 2, 3 pclkb 2 iclk 0008 9030h s12ad a/d data register 8 addr8 16 16 2, 3 pclkb 2 iclk 0008 9032h s12ad a/d data register 9 addr9 16 16 2, 3 pclkb 2 iclk 0008 9034h s12ad a/d data register 10 addr10 16 16 2, 3 pclkb 2 iclk 0008 9036h s12ad a/d data register 11 addr11 16 16 2, 3 pclkb 2 iclk 0008 9038h s12ad a/d data register 12 addr12 16 16 2, 3 pclkb 2 iclk 0008 903ah s12ad a/d data register 13 addr13 16 16 2, 3 pclkb 2 iclk 0008 903ch s12ad a/d data register 14 addr14 16 16 2, 3 pclkb 2 iclk 0008 903eh s12ad a/d data register 15 addr15 16 16 2, 3 pclkb 2 iclk 0008 9060h s12ad a/d sampling state register 0 adsstr0 8 8 2, 3 pclkb 2 iclk 0008 9061h s12ad a/d sampling state register l adsstrl 8 8 2, 3 pclkb 2 iclk 0008 9071h s12ad a/d sampling state register o adsstro 8 8 2, 3 pclkb 2 iclk 0008 9073h s12ad a/d sampling state register 1 adsstr1 8 8 2, 3 pclkb 2 iclk 0008 9074h s12ad a/d sampling state register 2 adsstr2 8 8 2, 3 pclkb 2 iclk 0008 9075h s12ad a/d sampling state register 3 adsstr3 8 8 2, 3 pclkb 2 iclk 0008 9076h s12ad a/d sampling state register 4 adsstr4 8 8 2, 3 pclkb 2 iclk 0008 9077h s12ad a/d sampling state register 5 adsstr5 8 8 2, 3 pclkb 2 iclk 0008 9078h s12ad a/d sampling state register 6 adsstr6 8 8 2, 3 pclkb 2 iclk 0008 9079h s12ad a/d sampling state register 7 adsstr7 8 8 2, 3 pclkb 2 iclk 0008 907ah s12ad a/d disconnecting detection control register addiscr 8 8 2, 3 pclkb 2 iclk 0008 a020h sci1 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a021h sci1 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a022h sci1 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a023h sci1 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a024h sci1 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a025h sci1 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a026h sci1 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a027h sci1 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a028h sci1 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a02ch sci1 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a02dh sci1 spi mode register spmr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (12 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 39 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 a0a0h sci5 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a0a1h sci5 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a0a2h sci5 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a0a3h sci5 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a0a4h sci5 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a0a5h sci5 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a0a6h sci5 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a0a7h sci5 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a0a8h sci5 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a0a9h sci5 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a0aah sci5 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a0abh sci5 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a0ach sci5 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a0adh sci5 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a0c0h sci6 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a0c1h sci6 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a0c2h sci6 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a0c3h sci6 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a0c4h sci6 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a0c5h sci6 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a0c6h sci6 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a0c7h sci6 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a0c8h sci6 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a0c9h sci6 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a0cah sci6 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a0cbh sci6 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a0cch sci6 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a0cdh sci6 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 a120h sci9 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 a121h sci9 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 a122h sci9 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 a123h sci9 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 a124h sci9 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 a125h sci9 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 a126h sci9 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 a127h sci9 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 a128h sci9 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 a129h sci9 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 a12ah sci9 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 a12bh sci9 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 a12ch sci9 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 a12dh sci9 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 b000h cac cac control register 0 cacr0 8 8 2, 3 pclkb 2 iclk 0008 b001h cac cac control register 1 cacr1 8 8 2, 3 pclkb 2 iclk 0008 b002h cac cac control register 2 cacr2 8 8 2, 3 pclkb 2 iclk 0008 b003h cac cac interrupt control register caicr 8 8 2, 3 pclkb 2 iclk 0008 b004h cac cac status register castr 8 8 2, 3 pclkb 2 iclk 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2, 3 pclkb 2 iclk 0008 b008h cac cac lower-limit value setting register callvr 16 16 2, 3 pclkb 2 iclk 0008 b00ah cac cac counter buffer register cacntbr 16 16 2, 3 pclkb 2 iclk 0008 b080h doc doc control register docr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (13 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 40 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 b082h doc doc data input register dodir 16 16 2, 3 pclkb 2 iclk 0008 b084h doc doc data setting register dodsr 16 16 2, 3 pclkb 2 iclk 0008 b100h elc event link control register elcr 8 8 2, 3 pclkb 2 iclk 0008 b102h elc event link setting register 1 elsr1 8 8 2, 3 pclkb 2 iclk 0008 b103h elc event link setting register 2 elsr2 8 8 2, 3 pclkb 2 iclk 0008 b104h elc event link setting register 3 elsr3 8 8 2, 3 pclkb 2 iclk 0008 b105h elc event link setting register 4 elsr4 8 8 2, 3 pclkb 2 iclk 0008 b10bh elc event link setting register 10 elsr10 8 8 2, 3 pclkb 2 iclk 0008 b10dh elc event link setting register 12 elsr12 8 8 2, 3 pclkb 2 iclk 0008 b110h elc event link setting register 15 elsr15 8 8 2, 3 pclkb 2 iclk 0008 b113h elc event link setting register 18 elsr18 8 8 2, 3 pclkb 2 iclk 0008 b115h elc event link setting register 20 elsr20 8 8 2, 3 pclkb 2 iclk 0008 b117h elc event link setting register 22 elsr22 8 8 2, 3 pclkb 2 iclk 0008 b119h elc event link setting register 24 elsr24 8 8 2, 3 pclkb 2 iclk 0008 b11ah elc event link setting register 25 elsr25 8 8 2, 3 pclkb 2 iclk 0008 b11fh elc event link option setting register a elopa 8 8 2, 3 pclkb 2 iclk 0008 b120h elc event link option setting register b elopb 8 8 2, 3 pclkb 2 iclk 0008 b122h elc event link option setting register d elopd 8 8 2, 3 pclkb 2 iclk 0008 b123h elc port group setting register 1 pgr1 8 8 2, 3 pclkb 2 iclk 0008 b125h elc port group control register 1 pgc1 8 8 2, 3 pclkb 2 iclk 0008 b127h elc port buffer register 1 pdbf1 8 8 2, 3 pclkb 2 iclk 0008 b129h elc event link port setting register 0 pel0 8 8 2, 3 pclkb 2 iclk 0008 b12ah elc event link port setting register 1 pel1 8 8 2, 3 pclkb 2 iclk 0008 b12dh elc event link software event generation register elsegr 8 8 2, 3 pclkb 2 iclk 0008 b300h sci12 serial mode register smr 8 8 2, 3 pclkb 2 iclk 0008 b301h sci12 bit rate register brr 8 8 2, 3 pclkb 2 iclk 0008 b302h sci12 serial control register scr 8 8 2, 3 pclkb 2 iclk 0008 b303h sci12 transmit data register tdr 8 8 2, 3 pclkb 2 iclk 0008 b304h sci12 serial status register ssr 8 8 2, 3 pclkb 2 iclk 0008 b305h sci12 receive data register rdr 8 8 2, 3 pclkb 2 iclk 0008 b306h sci12 smart card mode register scmr 8 8 2, 3 pclkb 2 iclk 0008 b307h sci12 serial extended mode register semr 8 8 2, 3 pclkb 2 iclk 0008 b308h sci12 noise filter setting register snfr 8 8 2, 3 pclkb 2 iclk 0008 b309h sci12 i 2 c mode register 1 simr1 8 8 2, 3 pclkb 2 iclk 0008 b30ah sci12 i 2 c mode register 2 simr2 8 8 2, 3 pclkb 2 iclk 0008 b30bh sci12 i 2 c mode register 3 simr3 8 8 2, 3 pclkb 2 iclk 0008 b30ch sci12 i 2 c status register sisr 8 8 2, 3 pclkb 2 iclk 0008 b30dh sci12 spi mode register spmr 8 8 2, 3 pclkb 2 iclk 0008 b320h sci12 extended serial mode enable register esmer 8 8 2, 3 pclkb 2 iclk 0008 b321h sci12 control register 0 cr0 8 8 2, 3 pclkb 2 iclk 0008 b322h sci12 control register 1 cr1 8 8 2, 3 pclkb 2 iclk 0008 b323h sci12 control register 2 cr2 8 8 2, 3 pclkb 2 iclk 0008 b324h sci12 control register 3 cr3 8 8 2, 3 pclkb 2 iclk 0008 b325h sci12 port control register pcr 8 8 2, 3 pclkb 2 iclk 0008 b326h sci12 interrupt control register icr 8 8 2, 3 pclkb 2 iclk 0008 b327h sci12 status register str 8 8 2, 3 pclkb 2 iclk 0008 b328h sci12 status clear register stcr 8 8 2, 3 pclkb 2 iclk 0008 b329h sci12 control field 0 data register cf0dr 8 8 2, 3 pclkb 2 iclk 0008 b32ah sci12 control field 0 compare enable register cf0cr 8 8 2, 3 pclkb 2 iclk 0008 b32bh sci12 control field 0 receive data register cf0rr 8 8 2, 3 pclkb 2 iclk 0008 b32ch sci12 primary control field 1 data register pcf1dr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (14 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 41 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 b32dh sci12 secondary control field 1 data register scf1dr 8 8 2, 3 pclkb 2 iclk 0008 b32eh sci12 control field 1 compare enable register cf1cr 8 8 2, 3 pclkb 2 iclk 0008 b32fh sci12 control field 1 receive data register cf1rr 8 8 2, 3 pclkb 2 iclk 0008 b330h sci12 timer control register tcr 8 8 2, 3 pclkb 2 iclk 0008 b331h sci12 timer mode register tmr 8 8 2, 3 pclkb 2 iclk 0008 b332h sci12 timer prescaler register tpre 8 8 2, 3 pclkb 2 iclk 0008 b333h sci12 timer count register tcnt 8 8 2, 3 pclkb 2 iclk 0008 c000h port0 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c001h port1 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c002h port2 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c003h port3 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c004h port4 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c005h port5 port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00ah porta port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00bh portb port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00ch portc port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00dh portd port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c00eh porte port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c011h porth port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c012h portj port direction register pdr 8 8 2, 3 pclkb 2 iclk 0008 c020h port0 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c021h port1 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c022h port2 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c023h port3 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c024h port4 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c025h port5 port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02ah porta port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02bh portb port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02ch portc port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02dh portd port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c02eh porte port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c031h porth port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c032h portj port output data register podr 8 8 2, 3 pclkb 2 iclk 0008 c040h port0 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c041h port1 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c042h port2 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing table 4.1 list of i/o register s (address order) (15 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 42 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 c043h port3 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c044h port4 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c045h port5 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04ah porta port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04bh portb port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04ch portc port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04dh portd port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c04eh porte port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pcl kb cy cles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c051h porth port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c052h portj port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 3 iclk cycles when reading, 2 iclk cycles when writing 0008 c060h port0 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c061h port1 port mode register pmr 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (16 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 43 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 c062h port2 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c063h port3 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c064h port4 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c065h port5 port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06ah porta port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06bh portb port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06ch portc port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06dh portd port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c06eh porte port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c071h porth port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c072h portj port mode register pmr 8 8 2, 3 pclkb 2 iclk 0008 c082h port1 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c083h port1 open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c085h port2 open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c086h port3 open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c087h port3 open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c094h porta open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c095h porta open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c096h portb open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c097h portb open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c098h portc open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c099h portc open drain control register 1 odr1 8 8, 16 2, 3 pclkb 2 iclk 0008 c09ch porte open drain control register 0 odr0 8 8, 16 2, 3 pclkb 2 iclk 0008 c0c0h port0 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c1h port1 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c2h port2 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c3h port3 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c4h port4 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0c5h port5 pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0cah porta pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0cbh portb pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0cch portc pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0cdh portd pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0ceh porte pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0d1h porth pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0d2h portj pull-up control register pcr 8 8 2, 3 pclkb 2 iclk 0008 c0e1h port1 drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0ebh portb drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c0ech portc drive capacity control register dscr 8 8 2, 3 pclkb 2 iclk 0008 c11fh mpc write-protect register pwpr 8 8 2, 3 pclkb 2 iclk 0008 c120h port port switching register b psrb 8 8 2, 3 pclkb 2 iclk 0008 c121h port port switching register a psra 8 8 2, 3 pclkb 2 iclk 0008 c147h mpc p07 pin function control register p07pfs 8 8 2, 3 pclkb 2 iclk 0008 c14ah mpc p12 pin function control register p12pfs 8 8 2, 3 pclkb 2 iclk 0008 c14bh mpc p13 pin function control register p13pfs 8 8 2, 3 pclkb 2 iclk 0008 c14ch mpc p14 pin function control register p14pfs 8 8 2, 3 pclkb 2 iclk 0008 c14dh mpc p15 pin function control register p15pfs 8 8 2, 3 pclkb 2 iclk 0008 c14eh mpc p16 pin function control register p16pfs 8 8 2, 3 pclkb 2 iclk 0008 c14fh mpc p17 pin function control register p17pfs 8 8 2, 3 pclkb 2 iclk 0008 c150h mpc p20 pin function control register p20pfs 8 8 2, 3 pclkb 2 iclk 0008 c151h mpc p21 pin function control register p21pfs 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (17 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 44 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 c152h mpc p22 pin function control register p22pfs 8 8 2, 3 pclkb 2 iclk 0008 c153h mpc p23 pin function control register p23pfs 8 8 2, 3 pclkb 2 iclk 0008 c154h mpc p24 pin function control register p24pfs 8 8 2, 3 pclkb 2 iclk 0008 c155h mpc p25 pin function control register p25pfs 8 8 2, 3 pclkb 2 iclk 0008 c156h mpc p26 pin function control register p26pfs 8 8 2, 3 pclkb 2 iclk 0008 c157h mpc p27 pin function control register p27pfs 8 8 2, 3 pclkb 2 iclk 0008 c158h mpc p30 pin function control register p30pfs 8 8 2, 3 pclkb 2 iclk 0008 c159h mpc p31 pin function control register p31pfs 8 8 2, 3 pclkb 2 iclk 0008 c15ah mpc p32 pin function control register p32pfs 8 8 2, 3 pclkb 2 iclk 0008 c15bh mpc p33 pin function control register p33pfs 8 8 2, 3 pclkb 2 iclk 0008 c15ch mpc p34 pin function control register p34pfs 8 8 2, 3 pclkb 2 iclk 0008 c160h mpc p40 pin function control register p40pfs 8 8 2, 3 pclkb 2 iclk 0008 c161h mpc p41 pin function control register p41pfs 8 8 2, 3 pclkb 2 iclk 0008 c162h mpc p42 pin function control register p42pfs 8 8 2, 3 pclkb 2 iclk 0008 c163h mpc p43 pin function control register p43pfs 8 8 2, 3 pclkb 2 iclk 0008 c164h mpc p44 pin function control register p44pfs 8 8 2, 3 pclkb 2 iclk 0008 c165h mpc p45 pin function control register p45pfs 8 8 2, 3 pclkb 2 iclk 0008 c166h mpc p46 pin function control register p46pfs 8 8 2, 3 pclkb 2 iclk 0008 c167h mpc p47 pin function control register p47pfs 8 8 2, 3 pclkb 2 iclk 0008 c16ch mpc p54 pin function control register p54pfs 8 8 2, 3 pclkb 2 iclk 0008 c16dh mpc p55 pin function control register p55pfs 8 8 2, 3 pclkb 2 iclk 0008 c190h mpc pa0 pin function control register pa0pfs 8 8 2, 3 pclkb 2 iclk 0008 c191h mpc pa1 pin function control register pa1pfs 8 8 2, 3 pclkb 2 iclk 0008 c192h mpc pa2 pin function control register pa2pfs 8 8 2, 3 pclkb 2 iclk 0008 c193h mpc pa3 pin function control register pa3pfs 8 8 2, 3 pclkb 2 iclk 0008 c194h mpc pa4 pin function control register pa4pfs 8 8 2, 3 pclkb 2 iclk 0008 c195h mpc pa5 pin function control register pa5pfs 8 8 2, 3 pclkb 2 iclk 0008 c196h mpc pa6 pin function control register pa6pfs 8 8 2, 3 pclkb 2 iclk 0008 c197h mpc pa7 pin function control register pa7pfs 8 8 2, 3 pclkb 2 iclk 0008 c198h mpc pb0 pin function control register pb0pfs 8 8 2, 3 pclkb 2 iclk 0008 c199h mpc pb1 pin function control register pb1pfs 8 8 2, 3 pclkb 2 iclk 0008 c19ah mpc pb2 pin function control register pb2pfs 8 8 2, 3 pclkb 2 iclk 0008 c19bh mpc pb3 pin function control register pb3pfs 8 8 2, 3 pclkb 2 iclk 0008 c19ch mpc pb4 pin function control register pb4pfs 8 8 2, 3 pclkb 2 iclk 0008 c19dh mpc pb5 pin function control register pb5pfs 8 8 2, 3 pclkb 2 iclk 0008 c19eh mpc pb6 pin function control register pb6pfs 8 8 2, 3 pclkb 2 iclk 0008 c19fh mpc pb7 pin function control register pb7pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a0h mpc pc0 pin function control register pc0pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a1h mpc pc1 pin function control register pc1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a2h mpc pc2 pin function control register pc2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a3h mpc pc3 pin function control register pc3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a4h mpc pc4 pin function control register pc4pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a5h mpc pc5 pin function control register pc5pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a6h mpc pc6 pin function control register pc6pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a7h mpc pc7 pin function control register pc7pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a8h mpc pd0 pin function control register pd0pfs 8 8 2, 3 pclkb 2 iclk 0008 c1a9h mpc pd1 pin function control register pd1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1aah mpc pd2 pin function control register pd2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1abh mpc pd3 pin function control register pd3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1ach mpc pd4 pin function control register pd4pfs 8 8 2, 3 pclkb 2 iclk 0008 c1adh mpc pd5 pin function control register pd5pfs 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (18 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 45 of 105 dec 20, 2013 rx220 group 4. i/o registers 0008 c1aeh mpc pd6 pin function control register pd6pfs 8 8 2, 3 pclkb 2 iclk 0008 c1afh mpc pd7 pin function control register pd7pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b0h mpc pe0 pin function control register pe0pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b1h mpc pe1 pin function control register pe1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b2h mpc pe2 pin function control register pe2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b3h mpc pe3 pin function control register pe3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b4h mpc pe4 pin function control register pe4pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b5h mpc pe5 pin function control register pe5pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b6h mpc pe6 pin function control register pe6pfs 8 8 2, 3 pclkb 2 iclk 0008 c1b7h mpc pe7 pin function control register pe7pfs 8 8 2, 3 pclkb 2 iclk 0008 c1c8h mpc ph0 pin function control register ph0pfs 8 8 2, 3 pclkb 2 iclk 0008 c1c9h mpc ph1 pin function control register ph1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1cah mpc ph2 pin function control register ph2pfs 8 8 2, 3 pclkb 2 iclk 0008 c1cbh mpc ph3 pin function control register ph3pfs 8 8 2, 3 pclkb 2 iclk 0008 c1d1h mpc pj1 pin function control register pj1pfs 8 8 2, 3 pclkb 2 iclk 0008 c1d3h mpc pj3 pin function control register pj3pfs 8 8 2, 3 pclkb 2 iclk 0008 c28fh system flash hoco software standby control register fhssbycr 8 8 4, 5 pclkb 2, 3 iclk 0008 c290h system reset status register 0 rstsr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c291h system reset status register 1 rstsr1 8 8 4, 5 pclkb 2, 3 iclk 0008 c293h system main clock oscillator forced oscillation control register mofcr 8 8 4, 5 pclkb 2, 3 iclk 0008 c294h system high-speed clock oscillator power su pply control register hocopcr 8 8 4, 5 pclkb 2, 3 iclk 0008 c296h flash flash write erase protection register fwepror 8 8 4, 5 pclkb 2, 3 iclk 0008 c297h system voltage monitoring circuit/comparator a control register lvcmpcr 8 8 4, 5 pclkb 2, 3 iclk 0008 c298h system voltage detection level select register lvdlvlr 8 8 4, 5 pclkb 2, 3 iclk 0008 c29ah system voltage monitoring 1 circuit/comparator a1 control register 0 lvd1cr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c29bh system voltage monitoring 2 circuit/comparator a2 control register 0 lvd2cr0 8 8 4, 5 pclkb 2, 3 iclk 0008 c400h rtc 64-hz counter r64cnt 8 8 2, 3 pclkb 2 iclk 0008 c402h rtc second counter/binary counter 0 rseccnt/ bcnt0 8 8 2, 3 pclkb 2 iclk 0008 c404h rtc minute counter/binary counter 1 rmincnt/ bcnt1 8 8 2, 3 pclkb 2 iclk 0008 c406h rtc hour counter/binary counter 2 rhrcnt/ bcnt2 8 8 2, 3 pclkb 2 iclk 0008 c408h rtc day-of-week counter/binary counter 3 rwkcnt/ bcnt3 8 8 2, 3 pclkb 2 iclk 0008 c40ah rtc date counter rdaycnt 8 8 2, 3 pclkb 2 iclk 0008 c40ch rtc month counter rmoncnt 8 8 2, 3 pclkb 2 iclk 0008 c40eh rtc year counter ryrcnt 16 16 2, 3 pclkb 2 iclk 0008 c410h rtc second alarm register/binary counter 0 alarm register rsecar/ bcnt0ar 8 8 2, 3 pclkb 2 iclk 0008 c412h rtc minute alarm register/binary counter 1 alarm register rminar/ bcnt1ar 8 8 2, 3 pclkb 2 iclk 0008 c414h rtc hour alarm register/binary counter 2 alarm register rhrar/ bcnt2ar 8 8 2, 3 pclkb 2 iclk 0008 c416h rtc day-of-week alarm register/binary counter 3 alarm register rwkar/ bcnt3ar 8 8 2, 3 pclkb 2 iclk 0008 c418h rtc date alarm register/binary counter 0 alarm enable register rdayar/ bcnt0aer 8 8 2, 3 pclkb 2 iclk 0008 c41ah rtc month alarm register/binary counter 1 alarm enable register rmonar/ bcnt1aer 8 8 2, 3 pclkb 2 iclk 0008 c41ch rtc year alarm register/binary counter 2 alarm enable register ryrar/ bcnt2aer 16 16 2, 3 pclkb 2 iclk 0008 c41eh rtc year alarm enable register/binary counter 3 alarm enable register ryraren/ bcnt3aer 8 8 2, 3 pclkb 2 iclk 0008 c422h rtc rtc control register 1 rcr1 8 8 2, 3 pclkb 2 iclk 0008 c424h rtc rtc control register 2 rcr2 8 8 2, 3 pclkb 2 iclk 0008 c426h rtc rtc control register 3 rcr3 8 8 2, 3 pclkb 2 iclk table 4.1 list of i/o register s (address order) (19 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 46 of 105 dec 20, 2013 rx220 group 4. i/o registers note 1. odd addresses cannot be accessed in 16-bit units. when accessing a register in 16-bit units, access the address of the t mr0 or tmr2 register. note 2. odd addresses cannot be accessed in 16-bit units. when accessing a register in 16-bit units, access the address of the t mocntl register. 0008 c42eh rtc time error adjustment register radj 8 8 2, 3 pclkb 2 iclk 007f c402h flash flash mode register fmodr 8 8 2, 3 fclk 2 iclk 007f c410h flash flash access status register fastat 8 8 2, 3 fclk 2 iclk 007f c411h flash flash access error interrupt enable register faeint 8 8 2, 3 fclk 2 iclk 007f c412h flash flash ready interrupt enable register frdyie 8 8 2, 3 fclk 2 iclk 007f c440h flash e2 dataflash read enable register 0 dflre0 16 16 2, 3 fclk 2 iclk 007f c450h flash e2 dataflash programming/erasure enable register 0 dflwe0 16 16 2, 3 fclk 2 iclk 007f ffb0h flash flash status register 0 fstatr0 8 8 2, 3 fclk 2 iclk 007f ffb1h flash flash status register 1 fstatr1 8 8 2, 3 fclk 2 iclk 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2, 3 fclk 2 iclk 007f ffb4h flash flash protection register fprotr 16 16 2, 3 fclk 2 iclk 007f ffb6h flash flash reset register fresetr 16 16 2, 3 fclk 2 iclk 007f ffbah flash fcu command register fcmdr 16 16 2, 3 fclk 2 iclk 007f ffc8h flash fcu processing switching register fcpsr 16 16 2, 3 fclk 2 iclk 007f ffcah flash e2 dataflash blank check control register dflbccnt 16 16 2, 3 fclk 2 iclk 007f ffcch flash flash p/e status register fpestat 16 16 2, 3 fclk 2 iclk 007f ffceh flash e2 dataflash blank check status register dflbcstat 16 16 2, 3 fclk 2 iclk 007f ffe8h flash peripheral clock notification register pckar 16 16 2, 3 fclk 2 iclk table 4.1 list of i/o register s (address order) (20 / 20) address module symbol register name register symbol number of bits access size number of access cycles iclk ? pclk iclk < pclk r01ds0130ej0110 rev.1.10 page 47 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the lsi may result if absolute maximum ratings are exceeded. to preclude any malfunctions due to noise interferences, insert capacitors of high frequency characteristics between the vcc and vss pins, between the avcc0 and avss0 pins, and between the vrefh0 and vrefl0 pins. place capacitors of 0.1 f or so as close to every power pin and use the shortest and heaviest possible traces. connect the vcl pin to a vss pin via a 0.1 f (20% accuracy) capacitor. the capacitor must be placed as close to the pin as possible. note 1. ports 12, 13, 16, and 17 are 5 v tolerant. note 2. set to the same potential as vcc. when the a/d converter is not used, do not leave the avcc0, vrefh0, avss0, and vrefl0 pins open. connect the avcc0 and vrefh0 pins to vcc, and the avss0 and vrefl0 pins to vss, respectively. note 3. the maximum value is 6.5 v. table 5.1 absolute maximum ratings conditions: vss = avss0 = vrefl0 = 0 v item symbol value unit power supply voltage vcc ?0.3 to +6.5 v input voltage (except for ports for 5v tolerant* 1 and port 4) v in ?0.3 to vcc +0.3* 3 v input voltage (port 4) v in ?0.3 to avcc0 +0.3* 3 v input voltage (ports for 5 v tolerant* 1 )v in ?0.3 to +6.5 v analog power supply voltage avcc0* 2 ?0.3 to +6.5 v reference power supply voltage vrefh0* 2 ?0.3 to avcc0 +0.3* 3 v analog input voltage (except for port 4) v an ?0.3 to vcc +0.3* 3 v analog input voltage (port 4) v an ?0.3 to avcc0 +0.3* 3 v operating temperature t opr ?40 to +105 c storage temperature t stg ?55 to +125 c r01ds0130ej0110 rev.1.10 page 48 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.2 dc characteristics table 5.2 dc characteristics (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage riic input pin (except for smbus, 5 v tolerant) v ih vcc 0.7 ? 5.8 v ports 12, 13, 16, and 17 (5 v tolerant) vcc 0.8 ? 5.8 ports 0, 14, 15, 2, 3, 4, 5, a, b, c, d, e, h, j, and res# vcc 0.8 ? vcc + 0.3 riic input pin (except for smbus) v il ?0.3 ? vcc 0.3 other than riic input pin ?0.3 ? vcc 0.2 riic input pin (except for smbus) ? v t vcc 0.05 ? ? other than riic input pin vcc 0.1 ? ? input level voltage (except for schmitt trigger input pins) md pin v ih vcc 0.9 ? vcc + 0.3 v extal vcc 0.8 ? vcc + 0.3 riic input pin (smbus) 2.1 ? vcc + 0.3 md pin v il ?0.3 ? vcc 0.1 extal ?0.3 ? vcc 0.2 riic input pin (smbus) ?0.3 ? 0.8 table 5.3 dc characteristics (2) conditions: vcc = avcc0 = 1.62 to 2.7 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage ports 12, 13, 16, and 17 (5 v tolerant) v ih vcc 0.8 ? 5.8 v ports 0, 14, 15, 2, 3, 4, 5, a, b, c, d, e, h, and j vcc 0.8 ? vcc + 0.3 res# vcc 0.9 ? vcc + 0.3 ports 0, 1, 2, 3, 4, 5, a, b, c, d, e, h, and j v il ?0.3 ? vcc 0.2 res# ?0.3 ? vcc 0.1 all input pins ? v t vcc 0.01 ? ? input level voltage (except for schmitt trigger input pins) md pin v ih vcc 0.9 ? vcc + 0.3 v extal vcc 0.8 ? vcc + 0.3 md pin v il ?0.3 ? vcc 0.1 extal ?0.3 ? vcc 0.2 r01ds0130ej0110 rev.1.10 page 49 of 105 dec 20, 2013 rx220 group 5. electrical characteristics table 5.4 dc characteristics (3) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions input leakage current res#, md pin, p35/nmi ? i in ? ??1.0av in = 0 v, vcc three-state leakage current (off-state) other pins except for ports for 5 v tolerant ? i tsi ? ??0.2av in = 0 v, vcc ports for 5 v tolerant ? ? 1.0 v in = 0 v, 5.8 v input capacitance all input pins (except for xcin and xcout) c in ? ? 15 pf v in = 0 v, f = 1 mhz, t a = 25c xcin and xcout ? ? 3 table 5.5 dc characteristics (4) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit test conditions 1.62 to 2.7 v 2.7 to 4.0 v 4.0 to 5.5 v min. max. min. max. min. max. input pull-up mos current all ports (except for port 35) i p ?150 ?5 ?200 ?10 ?400 ?50 a v in = 0 v r01ds0130ej0110 rev.1.10 page 50 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note 1. supply current values do not include output charge/disc harge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is hoco. bclk , fclk, and pclk are set to divided by 64. note 3. clocks are supplied to the peripher al functions. this does not include bgo opera tion. the clock source is hoco. bclk, fc lk, and pclk are iclk divided by 1. note 4. this is the increase if data is programmed to or er asing from the rom or e2 dataflash during program execution. table 5.6 dc characteristics (5) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ.* 9 max. unit test conditions supply current* 1 medium-speed operating modes 1a and 1b normal operating mode no peripheral operation* 2 iclk = 32 mhz i cc 4.6 ? ma iclk = 20 mhz 3.2 ? all peripheral operation: normal* 3 iclk = 32 mhz 14 ? iclk = 20 mhz 9.5 ? all peripheral operation: max.* 3 iclk = 32 mhz ? 25 iclk = 20 mhz ? 19 sleep mode no peripheral operation* 2 iclk = 32 mhz 3.8 ? iclk = 20 mhz 3.0 ? all peripheral operation: normal* 3 iclk = 32 mhz 10 ? iclk = 20 mhz 7 ? all-module clock stop mode iclk = 32 mhz 2.5 ? iclk = 20 mhz 2.0 ? increase during bgo operation* 4 medium-speed operating mode 1a 17 ? medium-speed operating mode 1b 17 ? low-speed operating mode 1 normal operating mode no peripheral operation* 5 iclk = 8 mhz 1.4 ? iclk = 4 mhz 0.9 ? iclk = 2 mhz 0.7 ? all peripheral operation: normal* 6 iclk = 8 mhz 4.2 ? iclk = 4 mhz 2.6 ? iclk = 2 mhz 1.8 ? all peripheral operation: max.* 6 iclk = 8 mhz ? 6.5 iclk = 4 mhz ? 3.7 iclk = 2 mhz ? 2.4 sleep mode no peripheral operation* 5 iclk = 8 mhz 1.5 ? iclk = 4 mhz 1.2 ? iclk = 2 mhz 1.1 ? all peripheral operation: normal* 6 iclk = 8 mhz 3.1 ? iclk = 4 mhz 2.1 ? iclk = 2 mhz 1.5 ? all-module clock stop mode iclk = 8 mhz 1.4 ? iclk = 4 mhz 1.1 ? iclk = 2 mhz 1.0 ? low-speed operating mode 2 normal operating mode no peripheral operation* 7 iclk = 32 khz 0.027 ? all peripheral operation: normal* 8 iclk = 32 khz 0.04 ? all peripheral operation: max.* 8 iclk = 32 khz ? 0.23 sleep mode no peripheral operation* 7 iclk = 32 khz 0.024 ? all peripheral operation: normal* 8 iclk = 32 khz 0.034 ? all-module clock stop mode 0.016 ? r01ds0130ej0110 rev.1.10 page 51 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note 5. clock supply to the peripheral func tions is stopped. this does not include bgo operation. the clock source is hoco. bclk , fclk, and pclk are set to divided by 64. note 6. clocks are supplied to the peripher al functions. this does not include bgo opera tion. the clock source is hoco. bclk, fc lk, and pclk are iclk divided by 1. note 7. clock supply to the peri pheral functions is stopped. this does not include bgo operation. the clock source is the sub os cillation circuit. bclk, fclk, and pclk are set to divided by 64. note 8. clocks are supplied to the peripheral functions. this does not include bgo operat ion. the clock source is the sub oscill ation circuit. bclk, fclk, and pclk are iclk divided by 1. note 9. vcc = 3.3 v. figure 5.1 voltage dependency in medium-speed operating modes 1a and 1b (reference data) 0 5 10 15 20 25 3.0 4.0 5.0 6.0 1.0 2.0 vcc (v) icc (ma) t a = 25c, iclk = 20 mhz* 1 t a = 105c, iclk = 20 mhz* 2 t a = 105c, iclk = 32 mhz* 2 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. t a = 25c, iclk = 32 mhz* 1 r01ds0130ej0110 rev.1.10 page 52 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.2 voltage dependency in low-speed operating mode 1 (reference data) figure 5.3 voltage dependency in low-speed operating mode 2 (reference data) 3.0 4.0 5.0 6.0 1.0 2.0 0 1 2 3 4 5 6 7 vcc (v) icc (ma) t a = 25c, iclk = 8 mhz * 1 ta = 105c, iclk = 8 mhz * 2 note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. t a = 25c, iclk = 4 mhz * 1 t a = 105c, iclk = 4 mhz * 2 t a = 105c, iclk = 2 mhz * 2 t a = 25c, iclk = 2 mhz * 1 0 50 100 150 200 3.0 4.0 5.0 6.0 1.0 2.0 t a = 25c, iclk = 32.768 khz * 1 t a = 105c, iclk = 32.768 khz * 2 vcc (v) icc ( ?a) note 1. all peripheral operation is normal. this does not include bgo operation. average value of the tested middle samples during product evaluation. note 2. all peripheral operation is maximum. this does not include bgo operation. average value of the tested upper-limit samples during product evaluation. r01ds0130ej0110 rev.1.10 page 53 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note 1. supply current values are with all output pins unloaded and all input pull- up moss in the off state. note 2. the iwdt and lvd are stopped. note 3. vcc = 3.3 v. table 5.7 dc characteristics (6) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ.* 3 max. unit test conditions supply current* 1 software standby mode* 2 flash memory power supplied, hoco power supplied, por low power consumption function disabled (softcut bit = 000b) t a = 25c i cc 9.3 16.4 a t a = 55c 11.3 25 t a = 85c 16 62 t a = 105c 25 127 flash memory power not supplied, hoco power not supplied, por low power consumption function enabled (softcut bit = 11xb) t a = 25c 1.7 7.0 t a = 55c 2.6 15 t a = 85c 6.3 51 t a = 105c 14.2 115 increments produced by running voltage detection circuits and disabling the por low power consumption function 1.4 ? increment for rtc operation (low cl) 0.6 ? increment for rtc operation (standard cl) 1.4 ? r01ds0130ej0110 rev.1.10 page 54 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.4 voltage dependency in software standby mode (softcut bit = 11xb) (reference data) figure 5.5 temperature dependency in software standby mode (softcut bit = 11xb) (reference data) vcc (v) 1 10 100 2.53.54.55.5 1.5 3.0 4.0 5.0 6.0 2.0 icc ( ? a) t a =105c* 2 note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. t a =85c* 2 t a =105c* 1 t a =55c* 2 t a =85c* 1 t a =55c* 1 t a =25c* 2 t a =25c* 1 -50 -30 -10 10 30 50 70 90 0.1 1 10 100 icc ( ? a) note 1. average value of the tested middle samples during product evaluation. note 2. average value of the tested upper-limit samples during product evaluation. t a (c) vcc = 3.3 v* 2 vcc = 3.3 v* 1 r01ds0130ej0110 rev.1.10 page 55 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note: ? please contact renesas electronics sale s office for derating of operation under t a = +85c to +105c. derating is the systematic reduction of load for th e sake of improved reliability. note 1. total power dissipated by the entire chip (including output currents) table 5.8 dc characteristics (7) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. max. unit test conditions permissible total consumption power* 1 pd ? 350 mw t a = ?40 to 85c ? 150 85c < t a 105c table 5.9 dc characteristics (8) conditions: vcc = avcc0 = 1.62 to 5.5 v, vrefh0 = 1.62 to avcc0, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions analog power supply current during a/d conversion conversion time = 1.56 s ai cc ?1.03.0ma waiting for a/d conversion (all units) ? 0.2 3.0 a reference power supply current during a/d conversion conversion time = 1.56 s i refh0 ?0.10.2ma waiting for a/d conversion (all units) ? 0.2 0.4 a table 5.10 dc characteristics (9) conditions: vcc = avcc0, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions ram standby voltage v ram 1.62 ? ? v table 5.11 dc characteristics (10) conditions: vcc = avcc0 = 0 to 5.5 v, vrefh0 = 0 to avcc0, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions vcc rising gradient srvcc 0.02 ? 20 ms/v at cold start table 5.12 dc characteristics (11) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c the ripple voltage must meet the allowable ripple frequency f r(vcc) within the range between the vcc upper limit (5.5 v) and lower limit (1.62 v). when vcc change exceeds vcc 10%, the allowable voltage change rising/falling gradient dt/dvcc must be met. item symbol min. typ. max. unit test conditions allowable ripple frequency f r(vcc) ? ? 10 khz vcc 0.1 < v r(vcc) vcc 0.2 ? ? 1 mhz vcc 0.05 < v r(vcc) vcc 0.1 ??10mhz v r(vcc) vcc 0.05 allowable voltage change rising/ falling gradient dt/dvcc 1.0 ? ? ms/v when vcc change exceeds vcc 10% r01ds0130ej0110 rev.1.10 page 56 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.6 ripple waveform table 5.13 permissible output currents (1) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, when total power (mw) < 1000 ? 10 t a item symbol max. unit permissible output low current (average value per 1 pin) normal output mode i ol 4.0 ma high-drive output mode 16.0 permissible output low current (maximum value per 1 pin) normal output mode 4.0 ma high-drive output mode 16.0 permissible output low current (t otal) total of all output pins ? i ol 80 ma permissible output high current (average value per 1 pin) normal output mode i oh ?4.0 ma high-drive output mode ?8.0 permissible output high current (maximum value per 1 pin) normal output mode ?4.0 ma high-drive output mode ?8.0 permissible output high current (t otal) total of all output pins ? i oh ?60 ma table 5.14 permissible output currents (2) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, when total power (mw) 1000 ? 10 t a item symbol max. unit permissible output low current (average value per 1 pin) normal output mode i ol 2.0 ma high-drive output mode 8.0 permissible output low current (maximum value per 1 pin) normal output mode 2.0 ma high-drive output mode 8.0 permissible output low current (t otal) total of all output pins ? i ol 40 ma permissible output high current (average value per 1 pin) normal output mode i oh ?2.0 ma high-drive output mode ?4.0 permissible output high current (maximum value per 1 pin) normal output mode ?2.0 ma high-drive output mode ?4.0 permissible output high current (t otal) total of all output pins ? i oh ?30 ma v r(vcc) vcc 1/f r(vcc) r01ds0130ej0110 rev.1.10 page 57 of 105 dec 20, 2013 rx220 group 5. electrical characteristics table 5.15 output valu es of voltage (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl0 = 0 v, when total power (mw) < 1000 ? 10 t a item symbol min. max. unit test conditions vcc = 2.7 to 4.0 v vcc = 4.0 to 5.5 v output low all output pins (other than riic) normal output mode v ol ?1.0vi ol = 3.0 ma i ol = 4.0 ma high-drive output mode ?1.0 i ol = 8.0 ma i ol = 16.0 ma riic pins ? 0.4 i ol = 3.0 ma ?0.6 i ol = 6.0 ma output high all output pins normal output mode v oh vcc ? 1.0 ? v i oh = ? 3.0 ma i oh = ? 4.0 ma high-drive output mode vcc ? 1.0 ? i oh = ? 5.0 ma i oh = ? 8.0 ma table 5.16 output valu es of voltage (2) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl0 = 0 v, when total power (mw) 1000 ? 10 t a item symbol min. max. unit test conditions vcc = 2.7 to 4.0 v vcc = 4.0 to 5.5 v output low all output pins (other than riic) normal output mode v ol ?1.0vi ol = 2.0 ma i ol = 2.0 ma high-drive output mode ?1.0 i ol = 8.0 ma i ol = 8.0 ma riic pins ? 0.4 i ol = 3.0 ma ?0.6 i ol = 6.0 ma output high all output pins normal output mode v oh vcc ? 1.0 ? v i oh = ? 2.0 ma i oh = ? 2.0 ma high-drive output mode vcc ? 1.0 ? i oh = ? 4.0 ma i oh = ? 4.0 ma table 5.17 output valu es of voltage (3) conditions: vcc = avcc0 = 1.62 to 2.7 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low all output pins (other than riic) normal output mode v ol ?0.4vi ol = 0.5 ma high-drive output mode ? 0.4 i ol = 2.0 ma output high all output pins normal output mode v oh vcc ? 0.4 ? v i oh = ?0.5 ma high-drive output mode vcc ? 0.4 ? i oh = ?1.0 ma r01ds0130ej0110 rev.1.10 page 58 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.2.1 standard i/o pin outp ut characteristics (1) figure 5.7 to figure 5.11 show the characteristics when normal output is selected by th e drive capacity control register. figure 5.7 v oh /v ol and i oh /i ol voltage characteristics at t a = 25c when normal output is selected (reference data) figure 5.8 v oh /v ol and i oh /i ol temperature characteristics at vcc = 1.62 v when normal output is selected (reference data) vcc = 5.5 v vcc = 5.5 v vcc = 3.3 v vcc = 2.7 v vcc = 2.7 v vcc = 1.62 v vcc = 1.62 v i oh /i ol vs v oh /v ol ?60 ?40 ?30 ?20 ?10 0 10 20 30 40 v oh /v ol [v] i oh /i ol [ma] vcc = 3.3 v 01 2 3 4 5 6 60 50 ?50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 t a = 105c t a = 25c t a = ?40c t a = ?40c t a = 25c t a = 105c r01ds0130ej0110 rev.1.10 page 59 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.9 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when normal output is selected (reference data) figure 5.10 v oh /v ol and i oh /i ol temperature characteristics at vcc = 3.3 v when normal output is selected (reference data) ?20 ?15 ?10 ?5 0 5 10 15 20 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] t a = 25c t a = ?40c t a = 105c t a = ?40c 2.5 0 0.5 1 1.5 2 3 t a = 25c t a = 105c ?30 ?20 ?10 10 20 30 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] t a = 25c t a = 105c t a = ?40c 2.5 0 0.5 1 1.5 2 3.5 t a = 25c t a = 105c 3 t a = ?40c 0 r01ds0130ej0110 rev.1.10 page 60 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.11 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when normal output is selected (reference data) i oh /i ol vs v oh /v ol ?60 ?40 ?30 ?20 ?10 0 10 20 30 40 v oh /v ol [v] i oh /i ol [ma] 01 2 3 4 5 6 60 50 ?50 t a = 25c t a = ?40c t a = 105c t a = 105 c t a = ?40c t a = 25c r01ds0130ej0110 rev.1.10 page 61 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.2.2 standard i/o pin outp ut characteristics (2) figure 5.12 to figure 5.16 show the characteristics when high-drive output is select ed by the drive capacity control register. figure 5.12 v oh /v ol and i oh /i ol voltage characteristics at t a = 25c when high-drive output is selected (reference data) figure 5.13 v oh /v ol and i oh /i ol temperature characteristics at vcc = 1.62 v when high-drive output is selected (reference data) vcc = 5.5 v vcc = 5.5 v vcc = 3.3 v vcc = 2.7 v vcc = 2.7 v vcc = 1.62 v vcc = 1.62 v i oh /i ol vs v oh /v ol ?120 ?80 ?60 ?40 ?20 0 20 40 60 80 v oh /v ol [v] i oh /i ol [ma] vcc = 3.3 v 01 2 3 4 5 6 120 100 ?100 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] t a = 25c t a = ?40c t a = 105c t a = 105c t a = ?40c t a = 25c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 ?12 ?8 ?6 ?4 ?2 0 2 4 6 8 12 10 ?10 r01ds0130ej0110 rev.1.10 page 62 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.14 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when high-drive output is selected (reference data) figure 5.15 v oh /v ol and i oh /i ol temperature characteristics at vcc = 3.3 v when high-drive output is selected (reference data) i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] t a = ?40c t a = 25c t a = 105c 0 0.5 1 1.5 2 2.5 3 t a = 105c t a = 25c t a = ?40c ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] t a = 25c t a = 105c t a = ?40c 2.5 0 0.5 1 1.5 2 3.5 t a = 105c 3 t a = ?40c ?60 ?40 ?20 20 40 60 0 50 30 10 ?10 ?30 ?50 t a = 25c r01ds0130ej0110 rev.1.10 page 63 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.16 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when high-drive output is selected (reference data) i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ?140 ?80 ?60 ?40 ?20 0 20 40 60 80 140 100 ?100 01 2 3 4 56 120 ?120 t a = 105c t a = ?40c t a = 25c t a = 105c t a = ?40c t a = 25c r01ds0130ej0110 rev.1.10 page 64 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.2.3 riic pin output characteristics figure 5.17 to figure 5.20 show the output characteristics of the riic pin. figure 5.17 v ol and i ol voltage characteristics of riic output pin at t a = 25c (reference data) figure 5.18 v ol and i ol temperature characteristics of riic output pin at vcc = 2.7 v (reference data) i ol vs v ol [v] v ol [v] i ol [ma] 01234 56 0 10 20 40 50 80 60 30 70 vcc = 5.5 v vcc = 3.3 v vcc = 2.7 v i ol vs v ol [v] v ol [v] i ol [ma] t a = 105c t a = 25c t a = ?40c 0 5 10 15 20 30 00.511.52 2.53 25 r01ds0130ej0110 rev.1.10 page 65 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.19 v ol and i ol temperature characteristics of riic output pin at vcc = 3.3 v (reference data) figure 5.20 v ol and i ol temperature characteristics of riic output pin at vcc = 5.5 v (reference data) i ol vs v ol [v] v ol [v] i ol [ma] 0 0.5 1 1.5 2 2.5 3.5 0 5 10 20 25 40 30 15 35 t a = 105c t a = 25c t a = ?40c 3 i ol vs v ol [v] v ol [v] i ol [ma] 01234 56 0 10 20 40 50 80 60 30 70 t a = 105c t a = 25c t a = ?40c r01ds0130ej0110 rev.1.10 page 66 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.3 ac characteristics note 1. the vcc is 2.7 to 5.5 v and the fclk must be running at a frequency of at least 4 mhz duri ng programming or erasing of t he flash memory. note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. note 1. the vcc is 1.62 to 3.6 v and the fclk must be running at a frequency of at least 4 mhz during programming or erasing of the flash memory. note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. note 1. programming and erasing the flash memory is impossible. note 2. the lower-limit frequency of pclkd is 1 mhz when the a/d converter is in use. note 1. programming and erasing the flash memory is impossible. note 2. the a/d converter cannot be used. table 5.18 operation frequency value (medium-speed operating mode 1a) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 883 2m h z flashif clock (fclk)* 1 883 2 peripheral module clock (pclkb) 8 8 32 peripheral module clock (pclkd)* 2 883 2 table 5.19 operation frequency value (medium-speed operating mode 1b) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 =vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 883 2m h z flashif clock (fclk)* 1 883 2 peripheral module clock (pclkb) 8 8 32 peripheral module clock (pclkd)* 2 883 2 table 5.20 operation frequency value (low-speed operating mode 1) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 248m h z flashif clock (fclk)* 1 248 peripheral module clock (pclkb) 2 4 8 peripheral module clock (pclkd)* 2 248 table 5.21 operation frequency value (low-speed operating mode 2) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol vcc unit 1.62 to 1.8 v 1.8 to 2.7 v 2.7 to 5.5 v maximum operating frequency system clock (iclk) f max 32.768 32.768 32.768 khz flashif clock (fclk)* 1 32.768 32.768 32.768 peripheral module clock (pclkb) 32.768 32.768 32.768 peripheral module clock (pclkd)* 2 32.768 32.768 32.768 r01ds0130ej0110 rev.1.10 page 67 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.3.1 clock timing note 1. the time interval from the time p36 and p37 are c onfigured for input and the main clock oscillator stopping bit (mosccr.mostp) is set to 0 (operating) until the clock becomes available. note 2. when specifying the main clock oscill ator stabilization time, load moscwtcr regi ster with a stabilization time value tha t is greater than the resonator-vendor-recommended value. when determining the main lock oscillation stabilization wait time, allow an adequate margin (2 times is recommended) for th e main clock oscillat ion stabilization time. start using the main clock in the main cl ock oscillation stabilization wait time (t mainoscwt) after setting up the main clock oscillator for operation with the mosccr.mostp bit. the indicated value is a reference value that is measured for an 8 mhz resonator. note 3. when specifying the sub-clock oscill ation stabilization time, load soscwtcr r egister with the resonator-vendor-recommend ed stabilization time value minus 2 seconds. when determining the sub-clock oscillation stabilization wait time, allow an adequate margin (2 times is recommended) for the sub-clock oscillation st abilization time. start using t he sub-clock in the sub-clock oscillation stabilization wait ti me (tsuboscwt) after setting up the sub-clock os cillator for operation with the sosccr.sostp or rcr3.rtcen bit. table 5.22 clock timing conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions extal external clock input cycle time t excyc 50 ? ? ns figure 5.21 extal external clock input high pulse width t exh 20 ? ? ns extal external clock input low pulse width t exl 20 ? ? ns extal external clock rising time t exr ?? 5ns extal external clock falling time t exf ?? 5ns extal external clock input wait time* 1 t exwt 1??ms main clock oscillator oscillation frequency* 2 f main 1?20mhz main clock oscillation stabilization time (crystal)* 2 t mainosc ? 3 ? ms figure 5.22 main clock oscillati on stabilization time (ceramic resonator)* 2 t mainosc ?50?s main clock oscillation stabilization wait time (crystal)* 2 t mainoscwt ?6?ms main clock oscillation stabili zation wait time (ceramic resonator)* 2 t mainoscwt ? 100 ? s loco clock cycle time t cyc 7.27 8 8.89 s loco clock oscillation frequency f loco 112.5 125 137.5 khz loco clock oscillation stabilization wait time t locowt ? ? 20 s figure 5.23 hoco clock oscillation frequency f hoco 31.680 32 32.320 mhz t a = 0 to 50c 36.495 36.864 37.233 39.600 40 40.400 49.500 50 50.500 31.520 32 32.480 t a = -40 to 105c 36.311 36.864 37.417 39.400 40 40.600 49.250 50 50.750 hoco clock oscillati on stabilization time 1 t hoco1 ? ? 50 s figure 5.24 hoco clock oscillati on stabilization time 2 t hoco2 ? ? 10 s figure 5.25 hoco clock oscillation stabilization wait time t hocowt ? ? 20 s figure 5.25 hoco clock power supply stabilization time t hocop ? ? 350 s figure 5.26 sub-clock oscillator oscillation frequency f sub ? 32.768 ? khz sub-clock oscillation stabilization time* 3 t subosc 2 ? ? s figure 5.27 sub-clock oscillation stabilization wait time* 3 t suboscwt 4??s r01ds0130ej0110 rev.1.10 page 68 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.21 extal external clock input timing figure 5.22 main clock oscillation start timing figure 5.23 loco clock oscillation start timing figure 5.24 hoco clock oscillation start timing (after reset is canceled by setting the ofs1.hocoen bit to 0) t exh t excyc extal external clock input vcc 0.5 t exl t exr t exf main clock oscillator output mosccr.mostp t mainosc main clock t mainoscwt loco clock lococr.lcstp t locowt res# internal reset hoco clock ofs1.hocoen t hoco1 t reswt r01ds0130ej0110 rev.1.10 page 69 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.25 hoco clock oscillation start timi ng (oscillation is st arted by setting the hococr.hcstp bit) figure 5.26 hoco po wer control timing figure 5.27 sub-clock oscillation start timing hococr.hcstp t hocowt t hoco2 hoco clock hoco clock output internal power supply for hoco hocopcr.hocopcnt t hocop hococr.hcstp sub-clock oscillator output sosccr.sostp t subosc sub-clock t suboscwt r01ds0130ej0110 rev.1.10 page 70 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.3.2 reset timing figure 5.28 reset input timing at power-on figure 5.29 reset input timing table 5.23 reset timing conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions res# pulse width power-on t reswp 8 ? ? ms figure 5.28 software standby mode, low-speed operating modes 1 and 2 t resws 1 ? ? ms figure 5.29 programming or erasure of the rom or e2 dataflash memory or blank checking of the e2 dataflash memory t reswf 200 ? ? s other than above t resw 200 ? ? s wait time after res# cancellation t reswt ? ? 912 s figure 5.28 internal reset time (independent watchdog timer reset, software reset) t resw2 ??1.4ms vcc res# t reswp internal reset t reswt 1.55 v res# internal reset t reswt t resws, t reswf, t resw r01ds0130ej0110 rev.1.10 page 71 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.3.3 timing of recovery from low power consumption modes note 1. the recovery time varies depending on the state of each os cillator when the wait instruction is executed. the recovery t ime when multiple oscillators are operating varies depending on the oper ating state of the oscillators that are not selected as the system clock source, and depends on the time set in the wait control registers corresponding to the oscillators. note 2. the indicated value is measured for an 8 mhz crystal resonator. iclk is set to divided by 1. note 3. when rcr3.rtcen = 1, the time will be t he time set in the soscwtcr register minus 2 s. note 4. when the external cl ock frequency is 20 mhz. iclk is set to divided by 1. note 5. iclk is set to divided by 1. note 6. when the frequency is 50 mhz, hocowtcr2.hsts 2[4:0] = 10101b and iclk is set to divided by 2. when the frequency is 32 mhz, hocowtcr2.hsts2[4:0] = 10100b and iclk is set to divided by 1. figure 5.30 software standby mode cancellation timing table 5.24 timing of recovery from low power consumption modes conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time after cancellation of software standby mode (hoco power supplied) (softcut[2:0] bits = 000b)* 1 crystal resonator connected to main clock oscillator* 2 main clock oscillator operating t sbymc ? 3 ? ms figure 5.30 external clock input to main clock oscillator* 4 main clock oscillator operating t sbyex 7??s sub-clock oscillator operating* 5 t sbysc 2* 3 ??s hoco clock oscillator operating* 6 t sbyho ??50s loco clock oscillator operating* 5 t sbylo ??90s recovery time after cancellation of software standby mode (hoco power not supplied) (softcut[2:0] bits = 11xb)* 1 crystal resonator connected to main clock oscillator* 2 main clock oscillator operating t sbymc ? 3 ? ms figure 5.30 external clock input to main clock oscillator* 4 main clock oscillator operating t sbyex 40 ? ? s sub-clock oscillator operating* 5 t sbysc 2* 3 ??s hoco clock oscillator operating* 6 t sbyho ??0.8ms loco clock oscillator operating* 5 t sbylo ??90s oscillator iclk irq software standby mode t sbymc, t sbyex, t sbysc, t sbyho, t sbylo r01ds0130ej0110 rev.1.10 page 72 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.3.4 control signal timing note: ? 200 ns minimum in software standby mode. figure 5.31 nmi interrupt input timing figure 5.32 irq interrupt input timing table 5.25 control signal timing conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions nmi pulse width t nmiw 200 ? ? ns t c(pclkb) 2 200 ns, figure 5.31 t c(pclkb) 2 ? ? ns t c(pclkb) 2 > 200 ns, figure 5.31 irq pulse width t irqw 200 ? ? ns t c(pclkb) 2 200 ns, figure 5.32 t c(pclkb) 2 ? ? ns t c(pclkb) 2 > 200 ns, figure 5.32 nmi t nmiw irq t irqw r01ds0130ej0110 rev.1.10 page 73 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.3.5 timing of on-chi p peripheral modules note 1. t pcyc : pclkb cycle note 2. value when the drive capacity of cl ock output ports is set to normal output. note 3. value when the drive capacity of data output ports is set to normal output. note 4. t cac : cac count clock source cycle table 5.26 timing of on-chi p peripheral modules (1) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit* 1 test conditions i/o ports input data pulse width t prw 1.5 ? t pcyc figure 5.33 mtu input capture input pulse width single-edge setting t ticw 1.5 ? t pcyc figure 5.34 both-edge setting 2.5 ? timer clock pulse width single-edge setting t tckwh, t tckwl 1.5 ? t pcyc figure 5.35 both-edge setting 2.5 ? phase counting mode 2.5 ? poe poe# input pulse width t poew 1.5 ? t pcyc figure 5.36 8-bit timer timer clock pulse width single-edge setting t tmcwh, t tmcwl 1.5 ? t pcyc figure 5.37 both-edge setting 2.5 ? sci input clock cycle asynchronous t scyc 4?t pcyc figure 5.38 clock synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?2 0n s input clock fall time t sckf ?2 0n s output clock cycle* 2 asynchronous t scyc 16 ? t pcyc c = 30 pf figure 5.39 clock synchronous 4 ? output clock pulse width* 2 t sckw 0.4 0.6 t scyc output clock rise time* 2 t sckr ?2 0n s output clock fall time* 2 t sckf ?2 0n s transmit data delay time* 3 clock synchronous 2.7 v vcc 5.5 v t txd ?4 0n s 1.62 v vcc < 2.7 v ? 80 receive data setup time clock synchronous 2.7 v vcc 5.5 v t rxs 40 ? ns 1.62 v vcc < 2.7 v 80 ? receive data hold time clock synchronous t rxh 40 ? ns a/d converter trigger input pulse width t trgw 1.5 ? t pcyc figure 5.40 cac cacref input pulse width t pcyc t cac * 4 t cacref 4.5 t cac + 3 t pcyc ?ns t pcyc > t cac * 4 5 t cac + 6.5 t pcyc r01ds0130ej0110 rev.1.10 page 74 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note 1. t pcyc : pclkb cycle note 2. value when the drive capacity of cl ock output ports is set to normal output. table 5.27 timing of on-chi p peripheral modules (2) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit* 1 test conditions rspi rspck clock cycle* 2 master t spcyc 2 4096 t pcyc c = 30 pf figure 5.41 slave 8 4096 rspck clock high pulse width * 2 master t spckwh (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock low pulse width * 2 master t spckwl (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock rise/fall time* 2 output 2.7 v vcc 5.5 v t spckr , t spckf ?1 0n s 1.62 v vcc < 2.7 v ?2 0 input ?1 s data input setup time master t su 4 ? ns c = 30 pf figure 5.42 to figure 5.47 slave 20 ? t pcyc ? data input hold time master pclkb set to a division ratio other than divided by 2 t h t pcyc ?n s pclkb set to divided by 2 t hf 0? slave t h 20 + 2 t pcyc ? ssl setup time master t lead 18t spcyc slave 4 ? t pcyc ssl hold time master t lag 18t spcyc slave 4 ? t pcyc data output delay time master 2.7 v vcc 5.5 v t od ?1 4n s 1.62 v vcc < 2.7 v ?2 8 slave 2.7 v vcc 5.5 v ?3 t pcyc + 40 1.62 v vcc < 2.7 v ?3 t pcyc + 80 data output hold time master t oh 0?n s slave 0 ? successive transmission delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 4 t pcyc ? mosi and miso rise/ fall time output 2.7 v vcc 5.5 v t dr , t df ?1 0n s 1.62 v vcc < 2.7 v ?2 0 input ?1 s ssl rise/fall time output t sslr , t sslf ?2 0n s input ?1 s slave access time t sa ?4t pcyc c = 30 pf figure 5.45 and figure 5.47 slave output release time t rel ?3t pcyc r01ds0130ej0110 rev.1.10 page 75 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note 1. t pcyc : pclkb cycle note 2. value when the drive capacity of cl ock output ports is set to normal output. table 5.28 timing of on-chi p peripheral modules (3) conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) * 2 t spcyc 4 65536 t pcyc c = 30 pf figure 5.41 sck clock cycle input (slave) 6 65536 sck clock high pulse width * 2 t spckwh 0.4 0.6 t spcyc sck clock low pulse width * 2 t spckwl 0.4 0.6 t spcyc sck clock rise/fall time t spckr, t spckf ?20ns data input setup time 2.7 v vcc 5.5 v t su 40 ? ns c = 30 pf figure 5.42 to figure 5.47 1.62 v vcc < 2.7 v 80 ? data input hold time t h 40 ? ns ss input setup time t lead 6?t pcyc ss input hold time t lag 6?t pcyc data output delay time 2.7 v vcc 5.5 v t od ?40ns 1.62 v vcc < 2.7 v ? 80 data output hold time t oh 0?ns data rise/fall time t dr, t df ?20ns ss input rise/fall time t sslr, t sslf ?20ns slave access time t sa ?5t pcyc c = 30 pf figure 5.45 and figure 5.47 slave output release time t rel ?5t pcyc r01ds0130ej0110 rev.1.10 page 76 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note: ? t iiccyc : riic internal reference count clock (iic ) cycle note 1. the value in parentheses is used when icmr3.nf[1:0] are set to 11b while a digital filter is enabled with icfer.nfe = 1. note 2. c b indicates the total capacity of the bus line. table 5.29 timing of on-chi p peripheral modules (4) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss 0 = vrefl0 = 0 v, fpclkb = up to 32 mhz, t a = ?40 to +105c item symbol min.* 1, * 2 max. unit test conditions riic (standard mode, smbus) scl input cycle time t scl 6 (12) t iiccyc + 1300 ? ns figure 5.48 scl input high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl input low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda input rise time t sr ? 1000 ns scl, sda input fall time t sf ? 300 ns scl, sda input spike pulse removal time t sp 01 ( 5 ) t iiccyc ns sda input bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 1000 ? ns stop condition input setup time t stos 1000 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf riic (fast mode) scl input cycle time t scl 6 (12) t iiccyc + 600 ? ns figure 5.48 scl input high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl input low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda input rise time t sr 20 + 0.1c b 300 ns scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda input bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition input hold time t stah t iiccyc + 300 ? ns restart condition input setup time t stas 300 ? ns stop condition input setup time t stos 300 ? ns data input setup time t sdas t iiccyc + 50 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf r01ds0130ej0110 rev.1.10 page 77 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note: ? t pcyc : pclkb cycle note 1. c b indicates the total capacity of the bus line. note 2. this applies when the smr.cks[1:0] bits = 00b and the sn fr.nfcs[2:0] bits = 010b while the snfr.nfe bit = 1 and the digi tal filter is enabled. table 5.30 timing of on-chi p peripheral modules (5) conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl0 = 0 v, fpclkb = up to 32 mhz, t a = ?40 to +105c item symbol min.* 1 max. unit test conditions simple iic (standard mode) sda input rise time t sr ? 1000 ns figure 5.48 sda input fall time t sf ? 300 ns sda input spike pulse removal time t sp 04 t pcyc * 2 ns data input setup time t sdas 250 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf simple iic (fast mode) scl, sda input rise time t sr 20 + 0.1c b 300 ns figure 5.48 scl, sda input fall time t sf 20 + 0.1c b 300 ns scl, sda input spike pulse removal time t sp 04 t pcyc * 2 ns data input setup time t sdas 100 ? ns data input hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf r01ds0130ej0110 rev.1.10 page 78 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.33 i/o port input timing figure 5.34 mtu input/output timing figure 5.35 mtu clock input timing figure 5.36 poe# input timing port pclk t prw output compare output input capture input pclk t ticw mtclka to mtclkd pclk t tckwl t tckwh poen# input pclk t poew r01ds0130ej0110 rev.1.10 page 79 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.37 8-bit timer clock input timing figure 5.38 sck clock input timing figure 5.39 sci input/output timing: clock synchronous mode figure 5.40 a/d converter external trigger input timing pclk tmci0 to tmci3 t tmcwl t tmcwh t sckw t sckr t sckf t scyc sckn (n = 1, 5, 6, 9, 12) t txd t rxs t rxh txdn rxdn sckn n = 1, 5, 6, 9, 12 adtrg0# pclk t trgw r01ds0130ej0110 rev.1.10 page 80 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.41 rspi clock timing and simple spi clock timing sckn master select output sckn slave select input (n = 1, 5, 6, 9, 12) t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc rspcka master select output rspcka slave select input simple spi rspi r01ds0130ej0110 rev.1.10 page 81 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.42 rspi timing (master, cpha = 0) (b it rate: pclkb set to division ratio other than divided by 2) and simple sp i timing (master, ckph = 1) figure 5.43 rspi timing (master, cpha = 0) (bit rate: pclkb set to divided by 2) t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output (n = 1, 5, 6, 9, 12) simple spi rspi ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output lsb in t dr, t df t su t hf t lead t td t lag t sslr, t sslf t oh t od msb in msb out data lsb out idle msb out msb in data t hf r01ds0130ej0110 rev.1.10 page 82 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.44 rspi timing (master, cpha = 1) (b it rate: pclkb set to division ratio other than divided by 2) and simple sp i timing (master, ckph = 0) figure 5.45 rspi timing (master, cpha = 1) (bit rate: pclkb set to divided by 2) t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output (n = 1, 5, 6, 9, 12) simple spi rspi ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output t dr, t df t hf t lead t td t lag t sslr, t sslf t oh data msb in msb out data lsb out idle msb out t od ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output msb in lsb in t su t h r01ds0130ej0110 rev.1.10 page 83 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.46 rspi timing (slave, cpha = 0) and simple spi timing (slave, ckph = 1) figure 5.47 rspi timing (slave, cpha = 1) and simple spi timing (slave, ckph = 0) t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input rspi simplespi sckn ckpol = 0 input sckn ckpol = 1 input smison output smosin input (n = 1, 5, 6, 9, 12) ssn# input t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out sckn ckpol = 1 input sckn ckpol = 0 input smison output smosin input (n = 1, 5, 6, 9, 12) simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input r01ds0130ej0110 rev.1.10 page 84 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.48 riic bus interface input/output timing and simple iic bus interface input/output timing test conditions v ih = vcc 0.7, v il = vcc 0.3 sda scl v ih v il t stah t sclh t scll p *1 s *1 t sf t sr t scl t sdah t sdas t stas t sp t stos p *1 t buf sr *1 note 1. s, p, and sr indicate the following conditions, respectively. s : start condition p : stop condition sr : restart condition r01ds0130ej0110 rev.1.10 page 85 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.4 a/d conversion characteristics note: ? the characteristics apply when no pin functions other t han a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl differ ential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time and t he comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the value in parentheses indicates the sampling time. table 5.31 a/d conversion characteristics (1) conditions: vcc = avcc0 = 2.7 to 5.5 v, 2.7 vrefh0 5.5 v, avcc0 ? 0.9 v vrefh0 avcc0, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions a/d conversion clock frequency (fpclkd) 1 ? 32 mhz resolution ? ? 12 bit conversion time* 1 (operation at fpclkd = 32 mhz) permissible signal source impedance (max.) = 1 k ? 1.56 (0.652)* 2 ? ? s sampling in 20 states permissible signal source impedance (max.) = 5 k ? 3.29 (2.35)* 2 ? ? sampling in 75 states analog input capacitance ? ? 30 pf offset error ? 0.5 4.5 lsb high-precision channel 7.5 normal-precision channel full-scale error ? 0.75 4.5 lsb high-precision channel 7.5 normal-precision channel quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel ? 1.25 8.0 lsb normal-precision channel dnl differential nonlinearity error ? 1.0 ? lsb inl integral nonlinearity error ? 1.0 3.0 lsb high-precision channel ? 1.0 5.0 lsb normal-precision channel table 5.32 channel classification for a/d converter classification channel high-precision channel an000 to an007 it is disallowed to use pins an000 to an007 as digital outputs when the a/d converter is used. normal-precision channel an008 to an015 table 5.33 a/d internal reference voltage characteristics conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ? 40 to +105 item min. typ. max. unit test conditions a/d internal reference voltage 1.35 1.50 1.65 v r01ds0130ej0110 rev.1.10 page 86 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note: ? the characteristics apply when no pin functions other t han a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl differ ential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time and t he comparison time. as the test conditions, the number of sampl ing states is indicated. note 2. the value in parentheses indicates the sampling time. figure 5.49 internal equivalen t circuit of analog input pin table 5.34 a/d conversion characteristics (2) conditions: vcc = avcc0 = 1.62 to 3.6 v, 1.62 vrefh0 2.7 v, avcc0 ? 0.9 v vrefh0 avcc0, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions a/d conversion clock frequency (fpclkd) 1 ? 8 mhz resolution ? ? 12 bit conversion time* 1 (operation at fpclkd = 8 mhz) permissible signal source impedance (max.) = 1 k ? 5.25 (1.5)* 2 ? ? s sampling in 12 states permissible signal source impedance (max.) = 5 k ? 6.25 (2.5)* 2 ? ? sampling in 20 states analog input capacitance ? ? 30 pf offset error ? 0.5 7.5 lsb full-scale error ? 1.25 7.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 3.0 8.0 lsb dnl differential nonlinearity error ? 1.25 ? lsb inl integral nonlinearity error ? 1.5 5.0 lsb table 5.35 sampling time conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol typ. unit test conditions sampling time high-precision channel ts 0.208 + 0.417 r0 (k ? ) s figure 5.49 normal-precision channel r0 ani rx220 r01ds0130ej0110 rev.1.10 page 87 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.50 illustration of a/d converter characteristic terms absolute accuracy absolute accuracy is the difference between output code based on the theoretical a/d conversion characteristics, and the actual a/d conversion result. when measur ing absolute accuracy, the voltage at th e midpoint of the width of analog input voltage (1-lsb width), that can m eet the expectation of outp utting an equal code based on the theoretical a/d conversion characteristics, is us ed as an analog input voltage. for example, if 12-bit resolution is used and if reference voltage (vrefh0) = 5.12 v, then 1-lsb width becomes 1. 25 mv, and 0 mv, 1.25 mv, 2.5 mv, ... are used as analog input voltages. if analog input voltage is 10 mv, absolu te accuracy = 5 lsb means that the actua l a/d conversion result is in the range of 003h to 00dh though an output code, 008h, can be expect ed from the theoretical a/d conversion characteristics. integral nonlinearity error (inl) integral nonlinearity error is the maximum deviation between the ideal line when the meas ured offset and full-scale errors are zeroed, and the actual output code. integral nonlinearity error (inl) actual a/d conversion characteristic ideal a/d conversion characteristic analog input voltage offset error absolute accuracy differential nonlinearity error (dnl) full-scale error fffh 000h 0 ideal line of actual a/d conversion characteristic 1-lsb width for ideal a/d conversion characteristic differential nonlinearity error (dnl) 1-lsb width for ideal a/d conversion characteristic vrefh0 (full-scale) a/d converter output code r01ds0130ej0110 rev.1.10 page 88 of 105 dec 20, 2013 rx220 group 5. electrical characteristics differential nonlinearity error (dnl) differential nonlinearity error is the difference between 1-lsb width base d on the ideal a/d conver sion characteristics and the width of the actually output code. offset error offset error is the difference between a transition point of the ideal first output code and the actual first output code. full-scale error full-scale error is the differen ce between a transition point of the ideal last output code and the actual last output code. r01ds0130ej0110 rev.1.10 page 89 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.5 comparator characteristics note 1. vcc does not include ripple. note 2. when the digital filter is disabled. table 5.36 comparator characteristics conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions comparator a external standard voltage input range lvref 1.4 D vcc v external comparison voltage* 1 (cmpa1, cmpa2) input range vi ?0.3 D vcc + 0.3 v offset DD 50 150 mv comparator output delay time* 2 DD 3 D s at falling edge vi = lvref ? 110 mv D 2 D s at falling edge vi < lvref ? 1 v D 3 D s at rising edge vi = lvref + 160 mv D 1.5 D s at rising edge vi > lvref + 1 v comparator operating current icmpa D 0.5 D a vcc = 5.0 v r01ds0130ej0110 rev.1.10 page 90 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.6 power-on reset circuit and voltage detecti on circuit characteristics note: ? these characteristics apply when noise is not superimposed on the power supply. note 1. when the cpu is in a mode other than software standby mode, when the cpu transits to software standby mode with the fhssbycr.softcut[2] bit set to 0. note 2. when the cpu transits to software standby mode with the fhssbycr.softcut[2] bit set to 1. note 3. # in the symbol vdet0_# denotes the value of the ofs1.vdsel[1:0] bits. note 4. # in the symbol vdet1_# denotes the value of the lvdlvlr.lvd1lvl[3:0] bits. table 5.37 power-on reset circuit and voltage detection circuit characteristics (1) conditions: vcc = avcc, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) low power consumption function disabled* 1 v por 1.30 1.40 1.55 v figure 5.51 and figure 5.52 low power consumption function enabled* 2 1.00 1.20 1.45 voltage detection circuit (lvd0)* 3 v det0_0 3.65 3.80 3.95 v figure 5.53 v det0_1 2.70 2.80 2.90 v det0_2 1.80 1.90 2.00 v det0_3 1.62 1.72 1.82 voltage detection circuit (lvd1)* 4 v det1_0 4.00 4.15 4.30 v figure 5.54 at falling edge vcc v det1_1 3.85 4.00 4.15 v det1_2 3.70 3.85 4.00 v det1_3 3.55 3.70 3.85 v det1_4 3.40 3.55 3.70 v det1_5 3.25 3.40 3.55 v det1_6 3.10 3.25 3.40 v det1_7 2.95 3.10 3.25 v det1_8 2.85 2.95 3.05 v det1_9 2.70 2.80 2.90 v det1_a 2.55 2.65 2.75 v det1_b 2.40 2.50 2.60 v det1_c 2.25 2.35 2.45 v det1_d 2.10 2.20 2.30 v det1_e 1.95 2.05 2.15 v det1_f 1.80 1.90 2.00 r01ds0130ej0110 rev.1.10 page 91 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note: ? these characteristics apply when noise is not superimposed on the power supply. note 1. # in the symbol vdet2_# denotes the value of the lvdlvlr.lvd2lvl[3:0] bits. note 2. the minimum vcc down time indicates the time when vcc is below the minimum value of voltage detection levels v por , v det0 , v det1, and v det2 for the por/ lvd. table 5.38 power-on reset circuit and voltage detection circuit characteristics (2) conditions: vcc = avcc0, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions voltage detection level voltage detection circuit (lvd2)* 1 v det2_0 4.00 4.15 4.30 v figure 5.55 at falling edge vcc v det2_1 3.85 4.00 4.15 v det2_2 3.70 3.85 4.00 v det2_3 3.55 3.70 3.85 v det2_4 3.40 3.55 3.70 v det2_5 3.25 3.40 3.55 v det2_6 3.10 3.25 3.40 v det2_7 2.95 3.10 3.25 v det2_8 2.85 2.95 3.05 v det2_9 2.70 2.80 2.90 v det2_a 2.55 2.65 2.75 v det2_b 2.40 2.50 2.60 v det2_c 2.25 2.35 2.45 v det2_d 2.10 2.20 2.30 v det2_e 1.95 2.05 2.15 v det2_f 1.80 1.90 2.00 v cmpa2 1.18 1.33 1.48 exvccinp2 = 1 internal reset time power-on reset time t por ? 9 ? ms figure 5.52 voltage monitoring 0 reset time t lvd0 ? 9 ? figure 5.53 voltage monitoring 1 reset time t lvd1 ? 1.4 ? figure 5.54 voltage monitoring 2 reset time t lvd2 ? 1.4 ? figure 5.55 minimum vcc down time* 2 t voff 200 ? ? s figure 5.51 response delay time t det ? ? 200 s figure 5.52 lvd operation stabilization time (after lvd is enabled) td (e-a) ? ? 15 s figure 5.54 and figure 5.55 power-on reset enable time t w(por) 1 ? ? ms figure 5.52 vcc = 0.9 v or lower hysteresis width (lvd1 and lvd2) v lvh ? 100 ? mv when selection is from among vdetx_0 to 7. ? 50 ? when selection is from among vdetx_8 to f. r01ds0130ej0110 rev.1.10 page 92 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.51 voltage detection reset timing figure 5.52 power-on reset timing figure 5.53 voltage detection circuit timing (v det0 ) t voff t por t det t det v por vcc internal reset signal (active-low) v por 0.9 v t w(por) t por t det vcc *1 internal reset signal (active-low) note 1. t w(por) is the time required for a power-on reset to be enabled while the external power vcc is being held below the valid voltage (0.9 v). when vcc turns on, maintain t w(por) for 1 ms or more. v por t voff t lvd0 t det v det0 vcc internal reset signal (active-low) t det r01ds0130ej0110 rev.1.10 page 93 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.54 voltage detection circuit timing (v det1 ) figure 5.55 voltage detection circuit timing (v det2 ) t voff v det1 vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1 t voff v det2 vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2 r01ds0130ej0110 rev.1.10 page 94 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.7 oscillation stop detection timing figure 5.56 oscillation stop detection timing table 5.39 oscillation stop detection circuit characteristics conditions: vcc = avcc0 = 1.62 to 5.5 v, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions detection time t dr ? ? 1 ms figure 5.56 t dr main clock ostdsr.ostdf loco clock iclk r01ds0130ej0110 rev.1.10 page 95 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.8 rom (flash memory for code storage) characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogr am/ erase cycle is n times (n = 10000), erasing can be performed n times for each block. for instance, when 128-byte programming is performed 16 times for different addresses in 2-kbyte block an d then the entire block is erased, the reprogram/erase cycle i s counted as one. however, programming the same address for se veral times as one erasing is not enabled (overwriting is prohibited). note 2. this result is obtained from reliability testing. table 5.40 rom (flash memory for code storage) characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n pec 10000 ? ? times data hold time after 1000 times of n pec t drp 30* 2 ? ? year t a = +85c after 10000 times of n pec 1* 2 ? ? year table 5.41 rom (flash memory for code storage) characteristics (2) item symbol fclk = 4 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. peripheral clock notification command wait time t pcka ? ? 960 ? ? 120 s r01ds0130ej0110 rev.1.10 page 96 of 105 dec 20, 2013 rx220 group 5. electrical characteristics table 5.42 rom (flash memory for code storage) characteristics (3) medium-speed operating mode 1a conditions: vcc = avcc0 = 2.7 to 5.5 v, vss = avss0 = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time when n pec 100 times 2 bytes t p2 ? 0.19 4.3 ? 0.12 2.0 ms 8 bytes t p8 ? 0.19 4.4 ? 0.12 2.0 128 bytes t p128 ? 0.67 10.7 ? 0.41 4.8 programming time when n pec > 100 times 2 bytes t p2 ? 0.23 5.3 ? 0.15 2.5 ms 8 bytes t p8 ? 0.23 5.4 ? 0.15 2.5 128 bytes t p128 ? 0.80 13.2 ? 0.48 6.0 erasure time when n pec 100 times 2 kbytes t e2k ? 13.0 92.8 ? 10.5 29 ms erasure time when n pec > 100 times 2 kbytes t e2k ? 15.9 176.9 ? 12.8 60 ms suspend delay time during programming (in programming/erasure priority mode) t spd ??0 . 9??0 . 8m s first suspend delay time during programming (in suspend priority mode) t spsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t spsd2 ??0 . 9??0 . 8m s suspend delay time during erasing (in programming/erasure priority mode) t sed ??0 . 9??0 . 8m s first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? 220 ? ? 120 s second suspend delay ti me during erasing (in suspend priority mode) t sesd2 ??0 . 9??0 . 8m s fcu reset time t fcur 20 s or longer and fclk 6 or greater ? ? 20 s or longer and fclk 6 or greater ?? s r01ds0130ej0110 rev.1.10 page 97 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note 1. the operating frequency is 8 mhz (max.) when the voltage is in the range from 1.62 v to less than 2.7 v. table 5.43 rom (flash memory for code storage) characteristics (4) medium-speed operating mode 1b conditions: vcc = avcc0 = 1.62 to 3.6 v, vss = avss0 = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz* 1 unit min. typ. max. min. typ. max. programming time when n pec 100 times 2 bytes t p2 ? 0.25 5.0 ? 0.21 2.8 ms 8 bytes t p8 ? 0.25 5.3 ? 0.21 3.0 128 bytes t p128 ? 0.92 14.0 ? 0.65 8.3 programming time when n pec > 100 times 2 bytes t p2 ? 0.31 6.2 ? 0.26 3.5 ms 8 bytes t p8 ? 0.31 6.6 ? 0.26 3.7 128 bytes t p128 ? 1.09 17.5 ? 0.77 10.0 erasure time when n pec 100 times 2 kbytes t e2k ? 21.0 113.6 ? 18.5 46 ms erasure time when n pec > 100 times 2 kbytes t e2k ? 25.6 220.6 ? 22.5 90 (1000 times n pec > 100 times), 98 (10000 times n pec > 1000 times) ms suspend delay time during programming (in programming/erasure priority mode) t spd ??1.7?? 1.6 ms first suspend delay time during programming (in suspend priority mode) t spsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t spsd2 ??1.7?? 1.6 ms suspend delay time during erasing (in programming/erasure priority mode) t sed ??1.7?? 1.6 ms first suspend delay time during erasing (in suspend priority mode) t sesd1 ? ? 220 ? ? 120 s second suspend delay time during erasing (in suspend priority mode) t sesd2 ??1.7?? 1.6 ms fcu reset time t fcur 20 s or longer and fclk 6 or greater ? ? 20 s or longer and fclk 6 or greater ?? s r01ds0130ej0110 rev.1.10 page 98 of 105 dec 20, 2013 rx220 group 5. electrical characteristics 5.9 e2 dataflash (flash memory fo r data storage) characteristics note 1. the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 100000 ), erasing can be performed n times for each block. for instance, when 8-byte programming is performed 16 times for different addresses in 128-byte block and then the entire block is eras ed, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (overwriting is prohibited). note 2. this result is obtained from reliability testing. table 5.44 e2 dataflash characteristics (1) item symbol min. typ. max. unit test conditions reprogramming/erasure cycle* 1 n dpec 100000 ? ? times data hold time after 100000 times of n dpec t drp 30* 2 ? ? year t a = +85c table 5.45 e2 dataflash characteristics (2) item symbol fclk = 4 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. peripheral clock notification command wait time t pcka ? ? 960 ? ? 120 s table 5.46 e2 dataflash characteristics (3) medium-speed operating mode 1a conditions: vcc = avcc0 = 2.7 to 5.5 v, vref h0 = avcc0, vss = avss0 = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time when n dpec 100 times 2 bytes t dp2 ? 0.19 4.4 ? 0.13 2.0 ms 8 bytes t dp8 ? 0.24 5.1 ? 0.13 2.2 programming time when n dpec > 100 times 2 bytes t dp2 ? 0.25 6.4 ? 0.17 3.0 ms 8 bytes t dp8 ? 0.32 7.5 ? 0.18 3.2 erasure time when n dpec 100 times 128 bytes t de128 ? 3.3 27.1 ? 2.5 8 ms erasure time when n dpec > 100 times 128 bytes t de128 ? 4.0 45.1 ? 3.0 12 ms blank check time 2 bytes t dbc2 ??98??35 s 2 kbytes t dbc2k ??16??2.5ms suspend delay time during programming (in programming/erasure priority mode) t dspd ??0.9??0.8ms first suspend delay time during programming (in suspend priority mode) t dspsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t dspsd2 ??0.9??0.8ms suspend delay time during erasing (in programming/erasure priority mode) t dsed ??0.9??0.8ms first suspend delay time during erasing (in suspend priority mode) t dsesd1 ? ? 220 ? ? 120 s second suspend delay ti me during erasing (in suspend priority mode) t dsesd2 ??0.9??0.8ms r01ds0130ej0110 rev.1.10 page 99 of 105 dec 20, 2013 rx220 group 5. electrical characteristics note 1. the operating frequency is 8 mhz (max.) when the voltage is in the range from 1.62 v to less than 2.7 v. table 5.47 e2 dataflash characteristics (4) medium-speed operating mode 1b conditions: vcc = avcc0 = 1.62 to 3.6 v, vss = avss0 = vrefl0 = 0 v temperature range for the programming/erasure operation: t a = ?40 to +105c item symbol fclk = 4 mhz fclk = 32 mhz* 1 unit min. typ. max. min. typ. max. programming time when n dpec 100 times 2 bytes t dp2 ? 0.28 5.1 ? 0.20 2.8 ms 8 bytes t dp8 ? 0.32 6.0 ? 0.22 3.2 programming time when n dpec > 100 times 2 bytes t dp2 ? 0.36 7.6 ? 0.25 4.2 ms 8 bytes t dp8 ? 0.40 8.8 ? 0.28 4.5 erasure time when n dpec 100 times 128 bytes t de128 ? 4.8 32.3 ? 4.1 12 ms erasure time when n dpec > 100 times 128 bytes t de128 ? 5.8 51.4 ? 4.9 17 ms blank check time 2 bytes t dbc2 ??110??40 s 2 kbytes t dbc2k ? ? 16.3 ? ? 2.6 ms suspend delay time during programming (in programming/erasure priority mode) t dspd ??1.7??1.6ms first suspend delay time during programming (in suspend priority mode) t dspsd1 ? ? 220 ? ? 120 s second suspend delay time during programming (in suspend priority mode) t dspsd2 ??1.7??1.6ms suspend delay time during erasing (in programming/erasure priority mode) t dsed ??1.7??1.6ms first suspend delay time during erasing (in suspend priority mode) t dsesd1 ? ? 220 ? ? 120 s second suspend delay ti me during erasing (in suspend priority mode) t dsesd2 ??1.7??1.6ms r01ds0130ej0110 rev.1.10 page 100 of 105 dec 20, 2013 rx220 group 5. electrical characteristics figure 5.57 flash memory pr ogram/erase suspend timing ? suspension during erasure fcu command fstatr0.frdy programming pulse ? suspension during programming program suspend ready not ready ready t spd programming fcu command fstatr0.frdy programming pulse ? suspension during programming ready not ready not ready t spsd1 fcu command fstatr0.frdy erasure pulse ? suspension during erasure erase suspend ready not ready ready t sed erasing in suspend priority mode in programming/erasure priority mode program suspend resume suspend resume suspend resume t spsd2 not ready t spsd1 programming programming programming application of the pulse stops application of the pulse continues fcu command erasure pulse ready not ready not ready t sesd1 erase suspend resume suspend resume suspend resume t sesd2 not ready t sesd1 erasing erasing erasing application of the pulse stops application of the pulse continues fstatr0.frdy r01ds0130ej0110 rev.1.10 page 101 of 105 dec 20, 2013 rx220 group appendix 1. package dimensions appendix 1. package dimensions information on the latest version of the package dimensions or mountings has been displayed in ?packages? on renesas electronics corporation. website. figure a 100-pin lqfp (plqp0100kb-a) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. index mark x 12 5 26 50 51 75 76 100 f *1 *3 *2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lfqfp100-14x14-0.50 e y s s r01ds0130ej0110 rev.1.10 page 102 of 105 dec 20, 2013 rx220 group appendix 1. package dimensions figure b 64-pin lqfp (plqp0064kb-a) terminal cross section b 1 c 1 b p c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension " *3" does not include trim offset. index mark *3 17 32 64 49 11 6 33 48 f *1 *2 x b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lfqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.250.200.15 maxnommin dimension in millimeters symbol reference 10.110.0 9.9 d 10.110.0 9.9 e 1.4 a 2 12.212.011.8 12.212.011.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s r01ds0130ej0110 rev.1.10 page 103 of 105 dec 20, 2013 rx220 group appendix 1. package dimensions figure c 64-pin lqfp (plqp0064ga-a) terminal cross section b1 c1 bp c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. *3 11 6 17 32 33 48 49 64 f *1 *2 x index mark d h d e h e e b p z d z e detail f c a a 2 a 1 l l 1 previous code jeita package code renesas code plqp0064ga-a 64p6u-a/ ? mass[typ.] 0.7g p-lqfp64-14x14-0.80 1.0 0.125 0.35 1.0 1.0 0.20 0.20 0.145 0.09 0.420.370.32 maxnom min dimension in millimeters symbol reference 14.1 14.0 13.9 d 14.1 14.0 13.9 e 1.4 a 2 16.2 16.0 15.8 16.2 16.0 15.8 1.7 a 0.2 0.1 0 0.70.50.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s r01ds0130ej0110 rev.1.10 page 104 of 105 dec 20, 2013 rx220 group appendix 1. package dimensions figure d 48-pin lqfp (plqp0048kb-a) terminal cross section b 1 c 1 bp c 2. 1. dimensions " *1" and "*2" do not include mold flash. note) dimension "*3" does not include trim offset. detail f l 1 c a l a 1 a 2 *3 f 48 37 36 25 24 13 12 1 *1 *2 x index mark z e z d b p e h e h d d e previous code jeita package code renesas code plqp0048kb-a 48p6q-a mass[typ.] 0.2g p-lfqfp48-7x7-0.50 1.0 0.125 0.20 0.75 0.75 0.08 0.20 0.145 0.09 0.270.220.17 maxnommin dimension in millimeters symbol reference 7.17.06.9 d 7.17.06.9 e 1.4 a 2 9.29.08.8 9.29.08.8 1.7 a 0.20.1 0 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s r01ds0130ej0110 rev.1.10 page 105 of 105 dec 20, 2013 rx220 group revision history revision history rx220 group datasheet rev. date description page summary 0.51 may 24, 2012 ? first edition, issued 1.00 dec 25, 2012 feature 1 irda, added low-power design and architecture, real-time cl ock, up to seven communications channels, operating temp. range, changed 1. overview 3, 4 table 1.1 outline of specifications: general i/o ports, event link controller (elc), realtime clock (rtcc), serial communications interfaces (scie, scif), irda, power supply voltage/ operating frequency, supply curr ent, operating temperature, changed 5 table 1.2 comparison of functi ons for different packages, changed 6 table 1.3 list of products, changed note 1, added 7 figure 1.1 how to read the product part no., memory capacity, and package type, changed 8 figure 1.2 block diagram, changed 9, 10 table 1.4 pin functions: power supply, on-chip emulator, serial communications interface (scie), changed 13 figure 1.4 pin assignments of the 64-pin lqfp, figure 1.5 pin assignments of the 48-pin lqfp, changed 14, 15 table 1.5 list of pins and pin functions (100-pin lqfp), chaned 17 table 1.6 list of pins and pi n functions (64-pin lqfp), chaned 19 table 1.7 list of pins and pi n functions (48-pin lqfp), chaned 4. i/o registers 32 to 46 table 4.1 list of i/o registers, changed notes 1 and 2, added 5. electrical characteristics 47 to 99 added 1.10 dec 20, 2013 all plqp0064ga-a 1414 mm, 0.8-mm pitch added features 1 operating temp. range changed 1. overview 4 table 1.1 outline of specifications changed, note 1 added 6 table 1.3 list of products changed, note added 7 figure 1.1 how to read the product part no., memory capacity, and package type changed 5. electrical characteristics 49 table 5.4 dc characteristics (3) changed 55 table 5.8 dc characteristics (7) added 56 table 5.13 permissible output currents (1) changed, table 5.14 permissible output currents (2) added 57 table 5.15 output values of voltage (1) changed, table 5.16 output values of voltage (2) added 73 table 5.26 timing of on-chip peripheral modules (1) changed 85 table 5.31 a/d conversion characteristics (1) changed 86 table 5.34 a/d conversion characteristics (2) changed 91 table 5.38 power-on reset circuit and voltage detection circuit char acteristics (2) changed all trademarks and registered trademarks are the property of thei r respective owners. revision history general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu pr oducts from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromag netic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal be come possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applie d to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset pr ocess is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provid ed for the possible future expansi on of functions. do not access these addresses; the correct operation of ls i is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program ex ecution, wait until the target clock signal has stabilized. ? when the clock signal is gene rated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only re leased after full stabilization of the clock signal. moreover, when switching to a clock signal produc ed with an external resonator (or by an external oscillator) while program ex ecution is in progress, wait until t he target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, ope rating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system-evaluation test for the given product. notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas e lectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatib ility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactu re, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or othe rwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesa s electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao rd., putuo district, shanghai, china tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-gu, seoul, 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2013 renesas electronics corporation. all rights reserved. colophon 3.0 |
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